57  * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
64  * SMBus Master core clock frequency. Timing configurations are
65  * strongly dependent on the core clock frequency of the SMBus
148  * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
151  *  SMBUS GW0 -> bits[26:25]
152  *  SMBUS GW1 -> bits[28:27]
153  *  SMBUS GW2 -> bits[30:29]
168  * Defines SMBus operating frequency and core clock frequency.
169  * According to ADB files, default values are compliant to 100KHz SMBus
185 /* SMBus timing parameters. */
205 /* SMBus Master GW. */
214 /* SMbus Master Finite State Machine. */
218 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */
242 /* SMBus master GW Data descriptor. */
246 /* Maximum bytes to read/write per SMBus transaction. */
271 /* SMBus slave GW. */
277 /* SMBus slave Finite State Machine (FSM). */
285 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
295 /* SMBus slave GW Data descriptor. */
299 /* SMbus slave configuration registers. */
420 	struct mlxbf_i2c_resource *smbus;  member
509 	 * de-asserted then the SMBus expects the following GW configuration  in mlxbf_i2c_smbus_transaction_success()
522  * Poll SMBus master status and return transaction status,
523  * i.e. whether succeeded or failed. I2C and SMBus fault codes
712 	 * Try to acquire the smbus gw lock before any reads of the GW register since  in mlxbf_i2c_smbus_start_transaction()
723 	 * SW must make sure that the SMBus Master GW is idle before starting  in mlxbf_i2c_smbus_start_transaction()
745 		 * then write command byte and set the optional SMBus specific  in mlxbf_i2c_smbus_start_transaction()
769 			 * as required for several SMBus and I2C operations.  in mlxbf_i2c_smbus_start_transaction()
777 		 * SMBus transaction. *TBD* protect this statement so it won't  in mlxbf_i2c_smbus_start_transaction()
821 		 * After a read operation the SMBus FSM ps (present state)  in mlxbf_i2c_smbus_start_transaction()
836 /* I2C SMBus protocols. */
1820  * Send byte to 'external' smbus master. This function is executed when
1821  * an external smbus master wants to read data from the BlueField.
1919  * Receive bytes from 'external' smbus master. This function is executed when
1920  * an external smbus master wants to write data to the BlueField.
1945 	 * Notify the slave backend that an smbus master wants to write data  in mlxbf_i2c_irq_recv()
2015 	 * specified in the SMBus standard, block transactions cannot exceed  in mlxbf_i2c_irq()
2048 		dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);  in mlxbf_i2c_smbus_xfer()
2055 		dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",  in mlxbf_i2c_smbus_xfer()
2062 		dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",  in mlxbf_i2c_smbus_xfer()
2069 		dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",  in mlxbf_i2c_smbus_xfer()
2085 		dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",  in mlxbf_i2c_smbus_xfer()
2106 		dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n",  in mlxbf_i2c_smbus_xfer()
2127 		dev_err(dev, "SMBus PEC and 10 bit address not supported\n");  in mlxbf_i2c_reg_slave()
2258 	 * Starting BlueField-3 SoC, the "smbus" resource was broken down into 3  in mlxbf_i2c_probe()
2279 		ret = mlxbf_i2c_init_resource(pdev, &priv->smbus,  in mlxbf_i2c_probe()
2282 			return dev_err_probe(dev, ret, "Cannot fetch smbus resource info");  in mlxbf_i2c_probe()
2284 		priv->timer->io = priv->smbus->io;  in mlxbf_i2c_probe()
2285 		priv->mst->io = priv->smbus->io + MLXBF_I2C_MST_ADDR_OFFSET;  in mlxbf_i2c_probe()
2286 		priv->slv->io = priv->smbus->io + MLXBF_I2C_SLV_ADDR_OFFSET;  in mlxbf_i2c_probe()
2344 		return dev_err_probe(dev, ret, "failed to initialize smbus master %d",  in mlxbf_i2c_probe()
2382 		params = priv->smbus->params;  in mlxbf_i2c_remove()