Lines Matching +full:fast +full:- +full:speed
1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #include "i2c-designware-core.h"
37 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
38 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
41 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
48 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
57 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
62 /* Set standard and fast speed dividers for high/low periods */ in i2c_dw_set_timings_master()
63 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
64 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
67 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
69 dev->ss_hcnt = in i2c_dw_set_timings_master()
76 dev->ss_lcnt = in i2c_dw_set_timings_master()
84 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
85 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
88 * Set SCL timing parameters for fast mode or fast mode plus. Only in i2c_dw_set_timings_master()
92 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { in i2c_dw_set_timings_master()
94 * Check are Fast Mode Plus parameters available. Calculate in i2c_dw_set_timings_master()
95 * SCL timing parameters for Fast Mode Plus if not set. in i2c_dw_set_timings_master()
97 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
98 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
99 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
102 dev->fs_hcnt = in i2c_dw_set_timings_master()
109 dev->fs_lcnt = in i2c_dw_set_timings_master()
120 * Calculate SCL timing parameters for fast mode if not set. They are in i2c_dw_set_timings_master()
121 * needed also in high speed mode. in i2c_dw_set_timings_master()
123 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
125 dev->fs_hcnt = in i2c_dw_set_timings_master()
132 dev->fs_lcnt = in i2c_dw_set_timings_master()
140 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
141 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
143 /* Check is high speed possible and fall back to fast mode if not */ in i2c_dw_set_timings_master()
144 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
148 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
149 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_set_timings_master()
150 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
151 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
152 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
153 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
154 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
160 * If dev->bus_capacitance_pF is greater than or equals in i2c_dw_set_timings_master()
164 if (dev->bus_capacitance_pF >= 400) { in i2c_dw_set_timings_master()
166 t_high = dev->clk_freq_optimized ? 160 : 120; in i2c_dw_set_timings_master()
171 t_low = dev->clk_freq_optimized ? 120 : 160; in i2c_dw_set_timings_master()
175 dev->hs_hcnt = in i2c_dw_set_timings_master()
182 dev->hs_lcnt = in i2c_dw_set_timings_master()
190 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
191 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
198 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); in i2c_dw_set_timings_master()
203 * i2c_dw_init_master() - Initialize the DesignWare I2C master hardware
223 /* Write standard speed timing parameters */ in i2c_dw_init_master()
224 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
225 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
227 /* Write fast mode/fast mode plus timing parameters */ in i2c_dw_init_master()
228 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
229 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
231 /* Write high speed timing parameters if supported */ in i2c_dw_init_master()
232 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
233 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
234 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
238 if (dev->sda_hold_time) in i2c_dw_init_master()
239 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
249 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
257 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
260 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
268 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
272 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
275 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
276 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
285 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
288 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
311 regmap_read(dev->map, DW_IC_STATUS, &status); in i2c_dw_is_controller_active()
315 return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, in i2c_dw_is_controller_active()
325 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, in i2c_dw_check_stopbit()
329 dev_err(dev->dev, "i2c timeout error %d\n", ret); in i2c_dw_check_stopbit()
362 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); in amd_i2c_dw_xfer_quirk()
364 dev->msgs = msgs; in amd_i2c_dw_xfer_quirk()
365 dev->msgs_num = num_msgs; in amd_i2c_dw_xfer_quirk()
366 dev->msg_write_idx = 0; in amd_i2c_dw_xfer_quirk()
375 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); in amd_i2c_dw_xfer_quirk()
381 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { in amd_i2c_dw_xfer_quirk()
382 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) in amd_i2c_dw_xfer_quirk()
387 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); in amd_i2c_dw_xfer_quirk()
388 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); in amd_i2c_dw_xfer_quirk()
390 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
391 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
402 regmap_read(dev->map, DW_IC_DATA_CMD, &val); in amd_i2c_dw_xfer_quirk()
410 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); in amd_i2c_dw_xfer_quirk()
431 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
434 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
435 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
436 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
442 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
443 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
450 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
451 dev_err(dev->dev, in i2c_dw_xfer_msg()
453 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
457 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
459 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
460 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
467 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
468 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
472 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
473 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
475 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
476 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
489 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
494 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
503 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
506 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
509 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
511 rx_limit--; in i2c_dw_xfer_msg()
512 dev->rx_outstanding++; in i2c_dw_xfer_msg()
514 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
517 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
520 dev->tx_buf = buf; in i2c_dw_xfer_msg()
521 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
531 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
536 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
539 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
546 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
549 if (dev->msg_err) in i2c_dw_xfer_msg()
558 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
559 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
567 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
568 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
569 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
572 * Received buffer length, re-enable TX_EMPTY interrupt in i2c_dw_recv_len()
585 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
588 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
593 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
596 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
597 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
598 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
600 len = dev->rx_buf_len; in i2c_dw_read()
601 buf = dev->rx_buf; in i2c_dw_read()
604 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
606 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
607 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
609 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
628 dev->rx_outstanding--; in i2c_dw_read()
632 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
633 dev->rx_buf_len = len; in i2c_dw_read()
634 dev->rx_buf = buf; in i2c_dw_read()
637 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
657 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_read_clear_intrbits()
658 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
660 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
661 stat &= dev->sw_mask; in i2c_dw_read_clear_intrbits()
669 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
672 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
674 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
676 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
678 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
684 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
685 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
688 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
690 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
692 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) in i2c_dw_read_clear_intrbits()
693 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
695 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
697 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
705 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_process_transfer()
706 dev->status &= ~STATUS_MASK; in i2c_dw_process_transfer()
707 dev->rx_outstanding = 0; in i2c_dw_process_transfer()
730 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && in i2c_dw_process_transfer()
731 (dev->rx_outstanding == 0)) in i2c_dw_process_transfer()
732 complete(&dev->cmd_complete); in i2c_dw_process_transfer()
733 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_process_transfer()
750 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
751 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
754 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0)) in i2c_dw_isr()
756 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
760 if (!(dev->status & STATUS_ACTIVE)) { in i2c_dw_isr()
779 unsigned long timeout = dev->adapter.timeout; in i2c_dw_wait_transfer()
783 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_wait_transfer()
784 ret = wait_for_completion_timeout(&dev->cmd_complete, timeout); in i2c_dw_wait_transfer()
788 ret = try_wait_for_completion(&dev->cmd_complete); in i2c_dw_wait_transfer()
801 return ret ? 0 : -ETIMEDOUT; in i2c_dw_wait_transfer()
813 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
815 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
817 switch (dev->flags & MODEL_MASK) { in i2c_dw_xfer()
825 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
826 dev->msgs = msgs; in i2c_dw_xfer()
827 dev->msgs_num = num; in i2c_dw_xfer()
828 dev->cmd_err = 0; in i2c_dw_xfer()
829 dev->msg_write_idx = 0; in i2c_dw_xfer()
830 dev->msg_read_idx = 0; in i2c_dw_xfer()
831 dev->msg_err = 0; in i2c_dw_xfer()
832 dev->status = 0; in i2c_dw_xfer()
833 dev->abort_source = 0; in i2c_dw_xfer()
834 dev->rx_outstanding = 0; in i2c_dw_xfer()
850 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
852 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
865 dev_err(dev->dev, "controller active\n"); in i2c_dw_xfer()
877 if (dev->msg_err) { in i2c_dw_xfer()
878 ret = dev->msg_err; in i2c_dw_xfer()
883 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
889 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
894 if (dev->status) in i2c_dw_xfer()
895 dev_err(dev->dev, in i2c_dw_xfer()
896 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
898 ret = -EIO; in i2c_dw_xfer()
904 pm_runtime_mark_last_busy(dev->dev); in i2c_dw_xfer()
905 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
921 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
923 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
925 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
928 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
930 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
932 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
935 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
938 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
948 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
957 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
963 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
964 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
967 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
971 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
973 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
976 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
978 rinfo->pinctrl = devm_pinctrl_get(dev->dev); in i2c_dw_init_recovery_info()
979 if (IS_ERR(rinfo->pinctrl)) { in i2c_dw_init_recovery_info()
980 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) in i2c_dw_init_recovery_info()
981 return PTR_ERR(rinfo->pinctrl); in i2c_dw_init_recovery_info()
983 rinfo->pinctrl = NULL; in i2c_dw_init_recovery_info()
984 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n"); in i2c_dw_init_recovery_info()
985 } else if (!rinfo->pinctrl) { in i2c_dw_init_recovery_info()
986 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n"); in i2c_dw_init_recovery_info()
989 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
990 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
991 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
992 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
994 dev_info(dev->dev, "running with GPIO recovery mode! scl%s", in i2c_dw_init_recovery_info()
995 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
1002 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
1007 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
1009 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
1034 ret = regmap_read(dev->map, DW_IC_CON, &ic_con); in i2c_dw_probe_master()
1040 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; in i2c_dw_probe_master()
1042 ret = dev->init(dev); in i2c_dw_probe_master()
1046 if (!adap->name[0]) in i2c_dw_probe_master()
1047 scnprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
1049 adap->retries = 3; in i2c_dw_probe_master()
1050 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
1051 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
1052 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
1055 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
1068 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_probe_master()
1069 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, in i2c_dw_probe_master()
1070 irq_flags, dev_name(dev->dev), dev); in i2c_dw_probe_master()
1072 dev_err(dev->dev, "failure requesting irq %i: %d\n", in i2c_dw_probe_master()
1073 dev->irq, ret); in i2c_dw_probe_master()
1088 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
1091 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
1092 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()