Lines Matching +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include "i2c-designware-core.h"
36 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
37 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
40 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
47 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
56 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
61 /* Set standard and fast speed dividers for high/low periods */ in i2c_dw_set_timings_master()
62 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
63 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
65 /* Calculate SCL timing parameters for standard mode if not set */ in i2c_dw_set_timings_master()
66 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
68 dev->ss_hcnt = in i2c_dw_set_timings_master()
76 dev->ss_lcnt = in i2c_dw_set_timings_master()
84 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
85 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
88 * Set SCL timing parameters for fast mode or fast mode plus. Only in i2c_dw_set_timings_master()
92 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) { in i2c_dw_set_timings_master()
94 * Check are Fast Mode Plus parameters available. Calculate in i2c_dw_set_timings_master()
95 * SCL timing parameters for Fast Mode Plus if not set. in i2c_dw_set_timings_master()
97 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
98 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
99 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
102 dev->fs_hcnt = in i2c_dw_set_timings_master()
110 dev->fs_lcnt = in i2c_dw_set_timings_master()
121 * Calculate SCL timing parameters for fast mode if not set. They are in i2c_dw_set_timings_master()
122 * needed also in high speed mode. in i2c_dw_set_timings_master()
124 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
126 dev->fs_hcnt = in i2c_dw_set_timings_master()
134 dev->fs_lcnt = in i2c_dw_set_timings_master()
142 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
143 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
145 /* Check is high speed possible and fall back to fast mode if not */ in i2c_dw_set_timings_master()
146 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
150 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
151 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_set_timings_master()
152 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
153 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
154 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
155 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
156 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
158 dev->hs_hcnt = in i2c_dw_set_timings_master()
166 dev->hs_lcnt = in i2c_dw_set_timings_master()
174 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
175 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
182 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); in i2c_dw_set_timings_master()
187 * i2c_dw_init_master() - Initialize the designware I2C master hardware
206 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
207 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
209 /* Write fast mode/fast mode plus timing parameters */ in i2c_dw_init_master()
210 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
211 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
214 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
215 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
216 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
220 if (dev->sda_hold_time) in i2c_dw_init_master()
221 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
231 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
239 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
242 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
243 * mode has to be enabled via bit 12 of IC_TAR register. in i2c_dw_xfer_init()
250 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
254 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
257 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
258 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
267 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
270 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
293 regmap_read(dev->map, DW_IC_STATUS, &status); in i2c_dw_is_controller_active()
297 return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, in i2c_dw_is_controller_active()
307 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val, in i2c_dw_check_stopbit()
311 dev_err(dev->dev, "i2c timeout error %d\n", ret); in i2c_dw_check_stopbit()
344 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN); in amd_i2c_dw_xfer_quirk()
346 dev->msgs = msgs; in amd_i2c_dw_xfer_quirk()
347 dev->msgs_num = num_msgs; in amd_i2c_dw_xfer_quirk()
356 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1); in amd_i2c_dw_xfer_quirk()
362 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) { in amd_i2c_dw_xfer_quirk()
363 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1) in amd_i2c_dw_xfer_quirk()
368 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100); in amd_i2c_dw_xfer_quirk()
369 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd); in amd_i2c_dw_xfer_quirk()
371 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
372 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1)); in amd_i2c_dw_xfer_quirk()
383 regmap_read(dev->map, DW_IC_DATA_CMD, &val); in amd_i2c_dw_xfer_quirk()
391 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd); in amd_i2c_dw_xfer_quirk()
412 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
415 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
416 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
417 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
423 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
424 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
431 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
432 dev_err(dev->dev, in i2c_dw_xfer_msg()
434 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
438 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
440 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
441 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
447 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
448 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
452 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
453 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
455 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
456 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
469 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
474 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
483 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
486 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
489 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
491 rx_limit--; in i2c_dw_xfer_msg()
492 dev->rx_outstanding++; in i2c_dw_xfer_msg()
494 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
497 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
500 dev->tx_buf = buf; in i2c_dw_xfer_msg()
501 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
511 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
516 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
519 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
526 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
529 if (dev->msg_err) in i2c_dw_xfer_msg()
538 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
539 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
547 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
548 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
549 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
552 * Received buffer length, re-enable TX_EMPTY interrupt in i2c_dw_recv_len()
565 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
568 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
573 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
576 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
577 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
578 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
580 len = dev->rx_buf_len; in i2c_dw_read()
581 buf = dev->rx_buf; in i2c_dw_read()
584 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
586 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
587 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
589 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
608 dev->rx_outstanding--; in i2c_dw_read()
612 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
613 dev->rx_buf_len = len; in i2c_dw_read()
614 dev->rx_buf = buf; in i2c_dw_read()
617 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
637 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_read_clear_intrbits()
638 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
640 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
641 stat &= dev->sw_mask; in i2c_dw_read_clear_intrbits()
649 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
652 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
654 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
656 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
658 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
664 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
665 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
668 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
670 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
672 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL))) in i2c_dw_read_clear_intrbits()
673 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
675 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
677 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
685 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_process_transfer()
686 dev->status &= ~STATUS_MASK; in i2c_dw_process_transfer()
687 dev->rx_outstanding = 0; in i2c_dw_process_transfer()
710 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) && in i2c_dw_process_transfer()
711 (dev->rx_outstanding == 0)) in i2c_dw_process_transfer()
712 complete(&dev->cmd_complete); in i2c_dw_process_transfer()
713 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_process_transfer()
730 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
731 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
734 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0)) in i2c_dw_isr()
736 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
740 if (!(dev->status & STATUS_ACTIVE)) { in i2c_dw_isr()
759 unsigned long timeout = dev->adapter.timeout; in i2c_dw_wait_transfer()
763 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_wait_transfer()
764 ret = wait_for_completion_timeout(&dev->cmd_complete, timeout); in i2c_dw_wait_transfer()
768 ret = try_wait_for_completion(&dev->cmd_complete); in i2c_dw_wait_transfer()
781 return ret ? 0 : -ETIMEDOUT; in i2c_dw_wait_transfer()
793 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
795 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
797 switch (dev->flags & MODEL_MASK) { in i2c_dw_xfer()
805 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
806 dev->msgs = msgs; in i2c_dw_xfer()
807 dev->msgs_num = num; in i2c_dw_xfer()
808 dev->cmd_err = 0; in i2c_dw_xfer()
809 dev->msg_write_idx = 0; in i2c_dw_xfer()
810 dev->msg_read_idx = 0; in i2c_dw_xfer()
811 dev->msg_err = 0; in i2c_dw_xfer()
812 dev->status = 0; in i2c_dw_xfer()
813 dev->abort_source = 0; in i2c_dw_xfer()
814 dev->rx_outstanding = 0; in i2c_dw_xfer()
830 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
832 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
845 dev_err(dev->dev, "controller active\n"); in i2c_dw_xfer()
857 if (dev->msg_err) { in i2c_dw_xfer()
858 ret = dev->msg_err; in i2c_dw_xfer()
863 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
869 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
874 if (dev->status) in i2c_dw_xfer()
875 dev_err(dev->dev, in i2c_dw_xfer()
876 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
878 ret = -EIO; in i2c_dw_xfer()
884 pm_runtime_mark_last_busy(dev->dev); in i2c_dw_xfer()
885 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
901 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
903 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
905 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
908 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
910 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
912 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
915 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
918 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
928 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
937 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
943 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
944 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
947 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
951 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
953 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
956 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
958 rinfo->pinctrl = devm_pinctrl_get(dev->dev); in i2c_dw_init_recovery_info()
959 if (IS_ERR(rinfo->pinctrl)) { in i2c_dw_init_recovery_info()
960 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) in i2c_dw_init_recovery_info()
961 return PTR_ERR(rinfo->pinctrl); in i2c_dw_init_recovery_info()
963 rinfo->pinctrl = NULL; in i2c_dw_init_recovery_info()
964 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n"); in i2c_dw_init_recovery_info()
965 } else if (!rinfo->pinctrl) { in i2c_dw_init_recovery_info()
966 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n"); in i2c_dw_init_recovery_info()
969 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
970 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
971 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
972 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
974 dev_info(dev->dev, "running with gpio recovery mode! scl%s", in i2c_dw_init_recovery_info()
975 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
982 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
987 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
989 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
1014 ret = regmap_read(dev->map, DW_IC_CON, &ic_con); in i2c_dw_probe_master()
1020 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; in i2c_dw_probe_master()
1022 ret = dev->init(dev); in i2c_dw_probe_master()
1026 snprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
1028 adap->retries = 3; in i2c_dw_probe_master()
1029 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
1030 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
1031 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
1034 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
1047 if (!(dev->flags & ACCESS_POLLING)) { in i2c_dw_probe_master()
1048 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, in i2c_dw_probe_master()
1049 irq_flags, dev_name(dev->dev), dev); in i2c_dw_probe_master()
1051 dev_err(dev->dev, "failure requesting irq %i: %d\n", in i2c_dw_probe_master()
1052 dev->irq, ret); in i2c_dw_probe_master()
1067 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
1070 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
1071 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()