Lines Matching +full:clk +full:- +full:freq +full:- +full:optimized
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk.h>
34 #include "i2c-designware-core.h"
64 "incorrect slave-transmitter mode configuration",
71 *val = readl(dev->base + reg); in dw_reg_read()
80 writel(val, dev->base + reg); in dw_reg_write()
89 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
98 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
107 *val = readw(dev->base + reg) | in dw_reg_read_word()
108 (readw(dev->base + reg + 2) << 16); in dw_reg_read_word()
117 writew(val, dev->base + reg); in dw_reg_write_word()
118 writew(val >> 16, dev->base + reg + 2); in dw_reg_write_word()
124 * i2c_dw_init_regmap() - Initialize registers map
151 if (dev->map) in i2c_dw_init_regmap()
158 reg = readl(dev->base + DW_IC_COMP_TYPE); in i2c_dw_init_regmap()
161 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) in i2c_dw_init_regmap()
171 dev_err(dev->dev, in i2c_dw_init_regmap()
173 return -ENODEV; in i2c_dw_init_regmap()
179 * basically we have MMIO-based regmap, so none of the read/write methods in i2c_dw_init_regmap()
182 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); in i2c_dw_init_regmap()
183 if (IS_ERR(dev->map)) { in i2c_dw_init_regmap()
184 dev_err(dev->dev, "Failed to init the registers map\n"); in i2c_dw_init_regmap()
185 return PTR_ERR(dev->map); in i2c_dw_init_regmap()
200 struct i2c_timings *t = &dev->timings; in i2c_dw_validate_speed()
208 if (t->bus_freq_hz == supported_speeds[i]) in i2c_dw_validate_speed()
212 dev_err(dev->dev, in i2c_dw_validate_speed()
214 t->bus_freq_hz); in i2c_dw_validate_speed()
216 return -EINVAL; in i2c_dw_validate_speed()
229 writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE, in mscc_twi_set_sda_hold_time()
230 dev->ext + MSCC_ICPU_CFG_TWI_DELAY); in mscc_twi_set_sda_hold_time()
240 switch (dev->flags & MODEL_MASK) { in i2c_dw_of_configure()
242 dev->ext = devm_platform_ioremap_resource(pdev, 1); in i2c_dw_of_configure()
243 if (!IS_ERR(dev->ext)) in i2c_dw_of_configure()
244 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; in i2c_dw_of_configure()
291 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { in i2c_dw_acpi_params()
292 const union acpi_object *objs = obj->package.elements; in i2c_dw_acpi_params()
305 struct i2c_timings *t = &dev->timings; in i2c_dw_acpi_configure()
312 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht); in i2c_dw_acpi_configure()
313 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht); in i2c_dw_acpi_configure()
314 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht); in i2c_dw_acpi_configure()
315 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht); in i2c_dw_acpi_configure()
317 switch (t->bus_freq_hz) { in i2c_dw_acpi_configure()
319 dev->sda_hold_time = ss_ht; in i2c_dw_acpi_configure()
322 dev->sda_hold_time = fp_ht; in i2c_dw_acpi_configure()
325 dev->sda_hold_time = hs_ht; in i2c_dw_acpi_configure()
329 dev->sda_hold_time = fs_ht; in i2c_dw_acpi_configure()
362 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); in i2c_dw_adjust_bus_speed()
363 struct i2c_timings *t = &dev->timings; in i2c_dw_adjust_bus_speed()
366 * Find bus speed from the "clock-frequency" device property, ACPI in i2c_dw_adjust_bus_speed()
369 if (acpi_speed && t->bus_freq_hz) in i2c_dw_adjust_bus_speed()
370 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); in i2c_dw_adjust_bus_speed()
371 else if (acpi_speed || t->bus_freq_hz) in i2c_dw_adjust_bus_speed()
372 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); in i2c_dw_adjust_bus_speed()
374 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_adjust_bus_speed()
379 struct i2c_timings *t = &dev->timings; in i2c_dw_fw_parse_and_configure()
380 struct device *device = dev->dev; in i2c_dw_fw_parse_and_configure()
385 if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus_capacitance_pF)) in i2c_dw_fw_parse_and_configure()
386 dev->bus_capacitance_pF = 100; in i2c_dw_fw_parse_and_configure()
388 dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized"); in i2c_dw_fw_parse_and_configure()
410 ret = regmap_read(dev->map, reg, &val); in i2c_dw_read_scl_reg()
436 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset; in i2c_dw_scl_hcnt()
456 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offset; in i2c_dw_scl_lcnt()
469 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®); in i2c_dw_set_sda_hold()
474 if (!dev->sda_hold_time) { in i2c_dw_set_sda_hold()
476 ret = regmap_read(dev->map, DW_IC_SDA_HOLD, in i2c_dw_set_sda_hold()
477 &dev->sda_hold_time); in i2c_dw_set_sda_hold()
485 * SCL by enabling non-zero SDA RX hold. Specification says it in i2c_dw_set_sda_hold()
489 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) in i2c_dw_set_sda_hold()
490 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; in i2c_dw_set_sda_hold()
492 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n", in i2c_dw_set_sda_hold()
493 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, in i2c_dw_set_sda_hold()
494 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); in i2c_dw_set_sda_hold()
495 } else if (dev->set_sda_hold_time) { in i2c_dw_set_sda_hold()
496 dev->set_sda_hold_time(dev); in i2c_dw_set_sda_hold()
497 } else if (dev->sda_hold_time) { in i2c_dw_set_sda_hold()
498 dev_warn(dev->dev, in i2c_dw_set_sda_hold()
500 dev->sda_hold_time = 0; in i2c_dw_set_sda_hold()
511 struct i2c_timings *t = &dev->timings; in __i2c_dw_disable()
519 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats); in __i2c_dw_disable()
520 regmap_read(dev->map, DW_IC_STATUS, &ic_stats); in __i2c_dw_disable()
521 regmap_read(dev->map, DW_IC_ENABLE, &enable); in __i2c_dw_disable()
527 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); in __i2c_dw_disable()
534 fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)); in __i2c_dw_disable()
539 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); in __i2c_dw_disable()
540 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, in __i2c_dw_disable()
544 dev_err(dev->dev, "timeout while trying to abort current transfer\n"); in __i2c_dw_disable()
553 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); in __i2c_dw_disable()
563 } while (timeout--); in __i2c_dw_disable()
565 dev_warn(dev->dev, "timeout in disabling adapter\n"); in __i2c_dw_disable()
574 if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) in i2c_dw_clk_rate()
576 return dev->get_clk_rate_khz(dev); in i2c_dw_clk_rate()
585 ret = clk_prepare_enable(dev->pclk); in i2c_dw_prepare_clk()
589 ret = clk_prepare_enable(dev->clk); in i2c_dw_prepare_clk()
591 clk_disable_unprepare(dev->pclk); in i2c_dw_prepare_clk()
596 clk_disable_unprepare(dev->clk); in i2c_dw_prepare_clk()
597 clk_disable_unprepare(dev->pclk); in i2c_dw_prepare_clk()
607 if (!dev->acquire_lock) in i2c_dw_acquire_lock()
610 ret = dev->acquire_lock(); in i2c_dw_acquire_lock()
614 dev_err(dev->dev, "couldn't acquire bus ownership\n"); in i2c_dw_acquire_lock()
621 if (dev->release_lock) in i2c_dw_release_lock()
622 dev->release_lock(); in i2c_dw_release_lock()
633 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, in i2c_dw_wait_bus_not_busy()
637 dev_warn(dev->dev, "timeout waiting for bus ready\n"); in i2c_dw_wait_bus_not_busy()
639 i2c_recover_bus(&dev->adapter); in i2c_dw_wait_bus_not_busy()
641 regmap_read(dev->map, DW_IC_STATUS, &status); in i2c_dw_wait_bus_not_busy()
651 unsigned long abort_source = dev->abort_source; in i2c_dw_handle_tx_abort()
656 dev_dbg(dev->dev, in i2c_dw_handle_tx_abort()
658 return -EREMOTEIO; in i2c_dw_handle_tx_abort()
662 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); in i2c_dw_handle_tx_abort()
665 return -EAGAIN; in i2c_dw_handle_tx_abort()
667 return -EINVAL; /* wrong msgs[] data */ in i2c_dw_handle_tx_abort()
669 return -EIO; in i2c_dw_handle_tx_abort()
679 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) { in i2c_dw_set_fifo_size()
680 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH; in i2c_dw_set_fifo_size()
681 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH; in i2c_dw_set_fifo_size()
694 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m); in i2c_dw_set_fifo_size()
701 if (!dev->tx_fifo_depth) { in i2c_dw_set_fifo_size()
702 dev->tx_fifo_depth = tx_fifo_depth; in i2c_dw_set_fifo_size()
703 dev->rx_fifo_depth = rx_fifo_depth; in i2c_dw_set_fifo_size()
705 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, in i2c_dw_set_fifo_size()
707 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, in i2c_dw_set_fifo_size()
718 return dev->functionality; in i2c_dw_func()
735 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_disable()
743 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); in i2c_dw_probe()
745 switch (dev->mode) { in i2c_dw_probe()
751 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); in i2c_dw_probe()
752 return -EINVAL; in i2c_dw_probe()
772 if (dev->shared_with_punit) in i2c_dw_runtime_suspend()
785 i2c_mark_adapter_suspended(&dev->adapter); in i2c_dw_suspend()
794 if (!dev->shared_with_punit) in i2c_dw_runtime_resume()
797 dev->init(dev); in i2c_dw_runtime_resume()
807 i2c_mark_adapter_resumed(&dev->adapter); in i2c_dw_resume()