34 #define CDNS_I2C_CR_HOLD		BIT(4) /* Hold Bus bit */
180  * @bus_hold_flag:	Flag used in repeated start for clearing HOLD bit
184  * @quirks:		flag for broken hold bit usage in r1p10
297  * cdns_i2c_clear_bus_hold - Clear bus hold bit
300  * Helper to clear the controller's bus hold bit.
503 				 * Clear hold bit that was set for FIFO control  in cdns_i2c_master_isr()
524 		 * register reaches zero without considering the HOLD bit.  in cdns_i2c_master_isr()
553 		/* Clear hold (if not repeated start) and signal completion */  in cdns_i2c_master_isr()
586 			 * clear the hold bus bit if there are no  in cdns_i2c_master_isr()
662 				 * Clear the hold bit that was set for FIFO control,  in cdns_i2c_mrecv_atomic()
677 		 * register reaches zero without considering the HOLD bit.  in cdns_i2c_mrecv_atomic()
707 	/* Clear hold (if not repeated start) */  in cdns_i2c_mrecv_atomic()
745 	 * 'hold bus' bit if it is greater than FIFO depth.  in cdns_i2c_mrecv()
770 	/* Determine hold_clear based on number of bytes to receive and hold flag */  in cdns_i2c_mrecv()
786 		 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size  in cdns_i2c_mrecv()
858 	 * 'hold bus' bit if it is greater than FIFO depth.  in cdns_i2c_msend()
887 	 * Clear the bus hold flag if there is no more data  in cdns_i2c_msend()
906  * This function cleanup the fifos, clear the hold bit and status
916 	/* Clear the hold bit and fifos */  in cdns_i2c_master_reset()
1040 		 * master receive message if HOLD bit is set (repeated start),  in cdns_i2c_master_common_xfer()