88 			drvdata->cmb->trig_patt[tpdm_attr->idx]);  in tpdm_simple_dataset_show()
93 			drvdata->cmb->trig_patt_mask[tpdm_attr->idx]);  in tpdm_simple_dataset_show()
98 			drvdata->cmb->patt_val[tpdm_attr->idx]);  in tpdm_simple_dataset_show()
103 			drvdata->cmb->patt_mask[tpdm_attr->idx]);  in tpdm_simple_dataset_show()
108 				drvdata->cmb->msr[tpdm_attr->idx]);  in tpdm_simple_dataset_show()
163 			drvdata->cmb->trig_patt[tpdm_attr->idx] = val;  in tpdm_simple_dataset_store()
169 			drvdata->cmb->trig_patt_mask[tpdm_attr->idx] = val;  in tpdm_simple_dataset_store()
175 			drvdata->cmb->patt_val[tpdm_attr->idx] = val;  in tpdm_simple_dataset_store()
181 			drvdata->cmb->patt_mask[tpdm_attr->idx] = val;  in tpdm_simple_dataset_store()
187 			drvdata->cmb->msr[tpdm_attr->idx] = val;  in tpdm_simple_dataset_store()
216 	if (drvdata && drvdata->cmb)  in tpdm_cmb_is_visible()
276 	if (drvdata->cmb)  in tpdm_reset_datasets()
277 		memset(drvdata->cmb, 0, sizeof(struct cmb_dataset));  in tpdm_reset_datasets()
391 	if (drvdata->cmb->patt_ts)  in set_cmb_tier()
395 	if (drvdata->cmb->trig_ts)  in set_cmb_tier()
399 	if (drvdata->cmb->ts_all)  in set_cmb_tier()
410 		writel_relaxed(drvdata->cmb->msr[i],  in set_cmb_msr()
418 	if (!drvdata->cmb)  in tpdm_enable_cmb()
423 		writel_relaxed(drvdata->cmb->patt_val[i],  in tpdm_enable_cmb()
425 		writel_relaxed(drvdata->cmb->patt_mask[i],  in tpdm_enable_cmb()
427 		writel_relaxed(drvdata->cmb->trig_patt[i],  in tpdm_enable_cmb()
429 		writel_relaxed(drvdata->cmb->trig_patt_mask[i],  in tpdm_enable_cmb()
438 	 * Set to 0 for continuous CMB collection mode,  in tpdm_enable_cmb()
439 	 * 1 for trace-on-change CMB collection mode.  in tpdm_enable_cmb()
441 	if (drvdata->cmb->trace_mode)  in tpdm_enable_cmb()
450 			drvdata->cmb->mcmb.trig_lane);  in tpdm_enable_cmb()
455 			drvdata->cmb->mcmb.lane_select);  in tpdm_enable_cmb()
458 	/* Set the enable bit of CMB control register to 1 */  in tpdm_enable_cmb()
467  * Continuous Multi-Bit(CMB), Multi-lane CMB(MCMB) and Discrete Single
526 	if (!drvdata->cmb)  in tpdm_disable_cmb()
530 	/* Set the enable bit of CMB control register to 0 */  in tpdm_disable_cmb()
592 			&& (!drvdata->cmb)) {  in tpdm_datasets_setup()
593 		drvdata->cmb = devm_kzalloc(drvdata->dev,  in tpdm_datasets_setup()
594 						sizeof(*drvdata->cmb), GFP_KERNEL);  in tpdm_datasets_setup()
595 		if (!drvdata->cmb)  in tpdm_datasets_setup()
616 	if (fwnode_property_present(dev->fwnode, "qcom,cmb-element-bits") &&  in static_tpdm_datasets_setup()
617 	    (!drvdata->cmb)) {  in static_tpdm_datasets_setup()
618 		drvdata->cmb = devm_kzalloc(drvdata->dev,  in static_tpdm_datasets_setup()
619 						sizeof(*drvdata->cmb), GFP_KERNEL);  in static_tpdm_datasets_setup()
621 		if (!drvdata->cmb)  in static_tpdm_datasets_setup()
842 				  (unsigned int)drvdata->cmb->patt_ts);  in enable_ts_show()
867 		drvdata->cmb->patt_ts = !!val;  in enable_ts_store()
981 	return sysfs_emit(buf, "%x\n", drvdata->cmb->trace_mode);  in cmb_mode_show()
997 	drvdata->cmb->trace_mode = trace_mode;  in cmb_mode_store()
1010 			  (unsigned int)drvdata->cmb->ts_all);  in cmb_ts_all_show()
1026 		drvdata->cmb->ts_all = true;  in cmb_ts_all_store()
1028 		drvdata->cmb->ts_all = false;  in cmb_ts_all_store()
1041 			  (unsigned int)drvdata->cmb->trig_ts);  in cmb_trig_ts_show()
1057 		drvdata->cmb->trig_ts = true;  in cmb_trig_ts_store()
1059 		drvdata->cmb->trig_ts = false;  in cmb_trig_ts_store()
1072 			  (unsigned int)drvdata->cmb->mcmb.trig_lane);  in mcmb_trig_lane_show()
1087 	drvdata->cmb->mcmb.trig_lane = val;  in mcmb_trig_lane_store()
1100 			  (unsigned int)drvdata->cmb->mcmb.lane_select);  in mcmb_lanes_select_show()
1115 	drvdata->cmb->mcmb.lane_select = val & TPDM_MCMB_E_LN_MASK;  in mcmb_lanes_select_store()
1411 					     "qcom,cmb-msrs-num", &drvdata->cmb_msr_num);  in tpdm_probe()