37 #define STMDMASTARTR			0xc04
38 #define STMDMASTOPR			0xc08
39 #define STMDMASTATR			0xc0c
40 #define STMDMACTLR			0xc10
41 #define STMDMAIDR			0xcfc
42 #define STMHEER				0xd00
43 #define STMHETER			0xd20
44 #define STMHEBSR			0xd60
45 #define STMHEMCR			0xd64
46 #define STMHEMASTR			0xdf4
47 #define STMHEFEAT1R			0xdf8
48 #define STMHEIDR			0xdfc
49 #define STMSPER				0xe00
50 #define STMSPTER			0xe20
51 #define STMPRIVMASKR			0xe40
52 #define STMSPSCR			0xe60
53 #define STMSPMSCR			0xe64
54 #define STMSPOVERRIDER			0xe68
55 #define STMSPMOVERRIDER			0xe6c
56 #define STMSPTRIGCSR			0xe70
57 #define STMTCSR				0xe80
58 #define STMTSSTIMR			0xe84
59 #define STMTSFREQR			0xe8c
60 #define STMSYNCR			0xe90
61 #define STMAUXCR			0xe94
62 #define STMSPFEAT1R			0xea0
63 #define STMSPFEAT2R			0xea4
64 #define STMSPFEAT3R			0xea8
65 #define STMITTRIGGER			0xee8
66 #define STMITATBDATA0			0xeec
67 #define STMITATBCTR2			0xef0
68 #define STMITATBID			0xef4
69 #define STMITATBCTR0			0xef8
79 #define STM_CHANNEL_OFFSET		0
82 	STM_PKT_TYPE_DATA	= 0x98,
83 	STM_PKT_TYPE_FLAG	= 0xE8,
84 	STM_PKT_TYPE_TRIG	= 0xF8,
158 	writel_relaxed(0x01 |	/* Enable HW event tracing */  in stm_hwevent_enable_hw()
159 		       0x04,	/* Error detection on event tracing */  in stm_hwevent_enable_hw()
169 	writel_relaxed(0x10,  in stm_port_enable_hw()
187 	writel_relaxed(0xFFF, drvdata->base + STMSYNCR);  in stm_enable_hw()
189 			0x02 |			 /* timestamp enable */  in stm_enable_hw()
190 			0x01),			 /* global STM enable */  in stm_enable_hw()
217 	return 0;  in stm_enable()
224 	writel_relaxed(0x0, drvdata->base + STMHEMCR);  in stm_hwevent_disable_hw()
225 	writel_relaxed(0x0, drvdata->base + STMHEER);  in stm_hwevent_disable_hw()
226 	writel_relaxed(0x0, drvdata->base + STMHETER);  in stm_hwevent_disable_hw()
235 	writel_relaxed(0x0, drvdata->base + STMSPER);  in stm_port_disable_hw()
236 	writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);  in stm_port_disable_hw()
248 	val &= ~0x1; /* clear global STM enable [0] */  in stm_disable_hw()
275 		coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);  in stm_disable()
374 		return 0;  in stm_mmio_addr()
406 	return 0;  in stm_generic_set_options()
431 			STM_FLAG_TIMESTAMPED : 0;  in stm_generic_packet()
433 			   STM_FLAG_GUARANTEED : 0;  in stm_generic_packet()
445 		 * The generic STM core sets a size of '0' on flag packets.  in stm_generic_packet()
454 		stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;  in stm_generic_packet()
482 	int ret = 0;  in hwevent_enable_store()
511 	int ret = 0;  in hwevent_select_store()
546 	int ret = 0;  in port_select_store()
559 		writel_relaxed(0x0, drvdata->base + STMSPER);  in port_select_store()
593 	int ret = 0;  in port_enable_store()
668 	int index = 0, found = 0;  in of_stm_get_stimulus_area()
706 	if (rc < 0)  in acpi_stm_get_stimulus_area()
721 			rc = 0;  in acpi_stm_get_stimulus_area()
761 	 * 0 - 32-bit data  in stm_fundamental_data_size()
773 	 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,  in stm_num_stimulus_port()
776 	numsp &= 0x1ffff;  in stm_num_stimulus_port()
785 	drvdata->stmspscr = 0x0;  in stm_init_default_data()
791 	drvdata->stmsper = ~0x0;  in stm_init_default_data()
794 	bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);  in stm_init_default_data()
835 	struct coresight_desc desc = { 0 };  in __stm_probe()
917 	if (trace_id < 0) {  in __stm_probe()
925 	return 0;  in __stm_probe()
971 	return 0;  in stm_runtime_suspend()
983 	return 0;  in stm_runtime_resume()
992 	CS_AMBA_ID_DATA(0x000bb962, "STM32"),
993 	CS_AMBA_ID_DATA(0x000bb963, "STM500"),
994 	{ 0, 0, NULL },
1012 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in stm_platform_probe()
1013 	int ret = 0;  in stm_platform_probe()
1042 	{"ARMHC502", 0, 0, 0}, /* ARM CoreSight STM */