Lines Matching defs:BANK_0
34 #define BANK_0 0x00
215 ret = nct7904_read_reg16(data, BANK_0,
239 ret = nct7904_read_reg(data, BANK_0,
295 ret = nct7904_read_reg16(data, BANK_0,
331 ret = nct7904_read_reg(data, BANK_0,
384 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
386 ret = nct7904_read_reg16(data, BANK_0,
389 ret = nct7904_read_reg16(data, BANK_0,
399 ret = nct7904_read_reg(data, BANK_0,
405 ret = nct7904_read_reg(data, BANK_0,
412 ret = nct7904_read_reg(data, BANK_0,
419 ret = nct7904_read_reg(data, BANK_0,
917 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
924 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
942 return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG,
958 ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
963 ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
968 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
976 ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
1016 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
1029 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
1032 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1038 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
1052 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1059 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
1097 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
1102 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
1118 ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);