Lines Matching refs:INA3221_MASK_ENABLE
37 #define INA3221_MASK_ENABLE 0x0f
81 [F_CVRF] = REG_FIELD(INA3221_MASK_ENABLE, 0, 0),
82 [F_WF3] = REG_FIELD(INA3221_MASK_ENABLE, 3, 3),
83 [F_WF2] = REG_FIELD(INA3221_MASK_ENABLE, 4, 4),
84 [F_WF1] = REG_FIELD(INA3221_MASK_ENABLE, 5, 5),
85 [F_SF] = REG_FIELD(INA3221_MASK_ENABLE, 6, 6),
86 [F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7),
87 [F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8),
88 [F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9),
121 * @summation_channel_control: Value written to SCC field in INA3221_MASK_ENABLE
751 regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE),
1002 ret = regmap_update_bits(ina->regmap, INA3221_MASK_ENABLE,