Lines Matching refs:div_l
156 u64 div_h, div_l, duty_cycle_period, dividend; in aspeed_pwm_get_state() local
163 div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val); in aspeed_pwm_get_state()
171 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1) in aspeed_pwm_get_state()
176 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt in aspeed_pwm_get_state()
192 u64 div_h, div_l, divisor, expect_period; in aspeed_pwm_apply() local
210 div_l = div64_u64(priv->clk_rate * expect_period, divisor); in aspeed_pwm_apply()
212 if (div_l == 0) in aspeed_pwm_apply()
215 div_l -= 1; in aspeed_pwm_apply()
217 if (div_l > 255) in aspeed_pwm_apply()
218 div_l = 255; in aspeed_pwm_apply()
221 priv->clk_rate, div_h, div_l); in aspeed_pwm_apply()
224 (u64)NSEC_PER_SEC * (div_l + 1) << div_h); in aspeed_pwm_apply()
258 FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) | in aspeed_pwm_apply()