Lines Matching refs:div_h
156 u64 div_h, div_l, duty_cycle_period, dividend; in aspeed_pwm_get_state() local
162 div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val); in aspeed_pwm_get_state()
172 << div_h; in aspeed_pwm_get_state()
177 << div_h; in aspeed_pwm_get_state()
192 u64 div_h, div_l, divisor, expect_period; in aspeed_pwm_apply() local
205 div_h = order_base_2(DIV64_U64_ROUND_UP(priv->clk_rate * expect_period, divisor)); in aspeed_pwm_apply()
206 if (div_h > 0xf) in aspeed_pwm_apply()
207 div_h = 0xf; in aspeed_pwm_apply()
209 divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h; in aspeed_pwm_apply()
221 priv->clk_rate, div_h, div_l); in aspeed_pwm_apply()
224 (u64)NSEC_PER_SEC * (div_l + 1) << div_h); in aspeed_pwm_apply()
257 val |= FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | in aspeed_pwm_apply()