Lines Matching +full:1 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
86 /* Touch Device Interrupt Cause register Format Configuration Register 1 */
90 /* THC Read PRD Base Address Low for the 1st RXDMA */
92 /* THC Read PRD Base Address High for the 1st RXDMA */
94 /* THC Read PRD Control for the 1st RXDMA */
96 /* THC Read DMA Control for the 1st RXDMA */
98 /* THC Read Interrupt Status for the 1st RXDMA */
100 /* THC Read DMA Error Register for the 1st RXDMA */
102 /* Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA */
104 /* Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA */
106 /* Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA */
108 /* Touch Host Controller GuC Control register for the 1st RXDMA */
110 /* Touch Sequencer Control for the 1st DMA */
112 /* Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA */
114 /* Touch Sequencer GuC Doorbell Address High for the 1st RXDMA */
118 /* Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA */
120 /* THC Device Address for the bulk/touch data read for the 1st RXDMA */
122 /* THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port */
124 /* THC Frame Count from the 1st Stream RXDMA on this port */
126 /* THC Micro Frame Count from the 1st Stream RXDMA on this port */
128 /* THC Packet Count from the 1st Stream RXDMA on this port */
131 * THC Software Interrupt Count from the 1st Stream RXDMA
135 /* Touch Sequencer Frame Drop Counter for the 1st RXDMA */
137 /* THC Coaescing 1 */
210 /* THC timing based Frame/Interrupt caolescing control register for 1st RXDMA */
214 /* Touch Sequencer PRD Table Empty Counter for the 1st RXDMA */
218 /* THC coalescing status to reflect the current coalescing FSM state for 1st RXDMA */
240 #define TXN_ERR_INT_STS_BIT BIT(28)
241 #define TXN_FATAL_INT_STS_BIT BIT(30)
243 #define NONDMA_INT_STS_BIT BIT(4)
244 #define EOF_INT_STS_BIT BIT(5)
249 #define THC_CFG_STS_CMD_IOSE BIT(0)
250 #define THC_CFG_STS_CMD_MSE BIT(1)
251 #define THC_CFG_STS_CMD_BME BIT(2)
252 #define THC_CFG_STS_CMD_SPCYC BIT(3)
253 #define THC_CFG_STS_CMD_MWRIEN BIT(4)
254 #define THC_CFG_STS_CMD_VGAPS BIT(5)
255 #define THC_CFG_STS_CMD_PERRR BIT(6)
256 #define THC_CFG_STS_CMD_SERREN BIT(8)
257 #define THC_CFG_STS_CMD_FBTBEN BIT(9)
258 #define THC_CFG_STS_CMD_INTD BIT(10)
259 #define THC_CFG_STS_CMD_INTS BIT(19)
260 #define THC_CFG_STS_CMD_CAPL BIT(20)
261 #define THC_CFG_STS_CMD_MCAP BIT(21)
262 #define THC_CFG_STS_CMD_FBTBC BIT(23)
263 #define THC_CFG_STS_CMD_MDPE BIT(24)
265 #define THC_CFG_STS_CMD_STA BIT(27)
266 #define THC_CFG_STS_CMD_RTA BIT(28)
267 #define THC_CFG_STS_CMD_RMA BIT(29)
268 #define THC_CFG_STS_CMD_SSE BIT(30)
269 #define THC_CFG_STS_CMD_DPE BIT(31)
279 #define THC_CFG_BIST_HTYPE_LT_CLS_MFD BIT(23)
281 #define THC_CFG_BAR0_LOW_MEMSPACE BIT(0)
282 #define THC_CFG_BAR0_LOW_TYP GENMASK(2, 1)
283 #define THC_CFG_BAR0_LOW_PREFETCH BIT(3)
296 #define THC_CFG_UR_STS_CTL_URRE BIT(0)
297 #define THC_CFG_UR_STS_CTL_URD BIT(1)
298 #define THC_CFG_UR_STS_CTL_FD BIT(2)
302 #define THC_CFG_MSIMC_MSINP_MSICID_MSIE BIT(16)
305 #define THC_CFG_MSIMC_MSINP_MSICID_XAC BIT(23)
306 #define THC_CFG_MSIMC_MSINP_MSICID_PVMC BIT(24)
314 #define THC_CFG_PMCAP_PMNP_PMCID_PMECLK BIT(19)
315 #define THC_CFG_PMCAP_PMNP_PMCID_DSI BIT(21)
317 #define THC_CFG_PMCAP_PMNP_PMCID_D1S BIT(25)
318 #define THC_CFG_PMCAP_PMNP_PMCID_D2S BIT(26)
321 #define THC_CFG_PMD_PMCSRBSE_PMCSR_PWRST GENMASK(1, 0)
322 #define THC_CFG_PMD_PMCSRBSE_PMCSR_NSR BIT(3)
323 #define THC_CFG_PMD_PMCSRBSE_PMCSR_PMEEN BIT(8)
326 #define THC_CFG_PMD_PMCSRBSE_PMCSR_PMESTS BIT(15)
338 #define THC_CFG_SWLTRPTR_VALID BIT(0)
339 #define THC_CFG_SWLTRPTR_BARNUM GENMASK(3, 1)
342 #define THC_CFG_DEVIDLEPTR_VALID BIT(0)
343 #define THC_CFG_DEVIDLEPTR_BARNUM GENMASK(3, 1)
348 #define THC_CFG_PCE_SPE BIT(0)
349 #define THC_CFG_PCE_I3E BIT(1)
350 #define THC_CFG_PCE_D3HE BIT(2)
351 #define THC_CFG_PCE_SE BIT(3)
352 #define THC_CFG_PCE_HAE BIT(5)
359 #define THC_M_CMN_DEVIDLECTRL_CIP BIT(0)
360 #define THC_M_CMN_DEVIDLECTRL_IR BIT(1)
361 #define THC_M_CMN_DEVIDLECTRL_DEVIDLE BIT(2)
362 #define THC_M_CMN_DEVIDLECTRL_RR BIT(3)
363 #define THC_M_CMN_DEVIDLECTRL_IRC BIT(4)
366 #define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_REQ BIT(0)
367 #define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_EN BIT(1)
368 #define THC_M_CMN_LTR_CTRL_LP_LTR_REQ BIT(2)
369 #define THC_M_CMN_LTR_CTRL_LP_LTR_EN BIT(3)
376 #define THC_M_PRT_CONTROL_TSFTRST BIT(0)
377 #define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_EN BIT(1)
378 #define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_HW_STS BIT(2)
379 #define THC_M_PRT_CONTROL_DEVRST BIT(3)
380 #define THC_M_PRT_CONTROL_THC_DRV_LOCK_EN BIT(13)
384 #define THC_M_PRT_CONTROL_THC_BIOS_LOCK_EN BIT(27)
385 #define THC_M_PRT_CONTROL_PORT_SUPPORTED BIT(28)
386 #define THC_M_PRT_CONTROL_SPI_IO_RDY BIT(29)
389 #define THC_M_PRT_SPI_CFG_SPI_TRDC GENMASK(1, 0)
395 #define THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN BIT(23)
404 #define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_INTERVAL_EN BIT(30)
405 #define THC_M_PRT_SPI_ICRRD_OPCODE_I2C_MAX_SIZE_EN BIT(31)
407 #define THC_M_PRT_INT_EN_SIPE BIT(0)
408 #define THC_M_PRT_INT_EN_SBO BIT(1)
409 #define THC_M_PRT_INT_EN_SIDR BIT(2)
410 #define THC_M_PRT_INT_EN_SOFB BIT(3)
411 #define THC_M_PRT_INT_EN_INVLD_DEV_ENTRY_INT_EN BIT(9)
412 #define THC_M_PRT_INT_EN_FRAME_BABBLE_ERR_INT_EN BIT(10)
413 #define THC_M_PRT_INT_EN_BUF_OVRRUN_ERR_INT_EN BIT(12)
414 #define THC_M_PRT_INT_EN_PRD_ENTRY_ERR_INT_EN BIT(13)
415 #define THC_M_PRT_INT_EN_DISP_SYNC_EVT_INT_EN BIT(14)
416 #define THC_M_PRT_INT_EN_DEV_RAW_INT_EN BIT(15)
417 #define THC_M_PRT_INT_EN_FATAL_ERR_INT_EN BIT(16)
418 #define THC_M_PRT_INT_EN_THC_I2C_IC_RX_UNDER_INT_EN BIT(17)
419 #define THC_M_PRT_INT_EN_THC_I2C_IC_RX_OVER_INT_EN BIT(18)
420 #define THC_M_PRT_INT_EN_THC_I2C_IC_RX_FULL_INT_EN BIT(19)
421 #define THC_M_PRT_INT_EN_THC_I2C_IC_TX_OVER_INT_EN BIT(20)
422 #define THC_M_PRT_INT_EN_THC_I2C_IC_TX_EMPTY_INT_EN BIT(21)
423 #define THC_M_PRT_INT_EN_THC_I2C_IC_TX_ABRT_INT_EN BIT(22)
424 #define THC_M_PRT_INT_EN_THC_I2C_IC_SCL_STUCK_AT_LOW_DET_INT_EN BIT(24)
425 #define THC_M_PRT_INT_EN_THC_I2C_IC_STOP_DET_INT_EN BIT(25)
426 #define THC_M_PRT_INT_EN_THC_I2C_IC_START_DET_INT_EN BIT(26)
427 #define THC_M_PRT_INT_EN_THC_I2C_IC_MST_ON_HOLD_INT_EN BIT(27)
428 #define THC_M_PRT_INT_EN_TXN_ERR_INT_EN BIT(29)
429 #define THC_M_PRT_INT_EN_GBL_INT_EN BIT(31)
431 #define THC_M_PRT_INT_STATUS_DISP_SYNC_EVT_INT_STS BIT(14)
432 #define THC_M_PRT_INT_STATUS_DEV_RAW_INT_STS BIT(15)
433 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_UNDER_INT_STS BIT(17)
434 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_OVER_INT_STS BIT(18)
435 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_FULL_INT_STS BIT(19)
436 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_OVER_INT_STS BIT(20)
437 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_EMPTY_INT_STS BIT(21)
438 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_ABRT_INT_STS BIT(22)
439 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_ACTIVITY_INT_STS BIT(23)
440 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_SCL_STUCK_AT_LOW_INT_STS BIT(24)
441 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_STOP_DET_INT_STS BIT(25)
442 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_START_DET_INT_STS BIT(26)
443 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_MST_ON_HOLD_INT_STS BIT(27)
444 #define THC_M_PRT_INT_STATUS_TXN_ERR_INT_STS BIT(28)
445 #define THC_M_PRT_INT_STATUS_FATAL_ERR_INT_STS BIT(30)
447 #define THC_M_PRT_ERR_CAUSE_INVLD_DEV_ENTRY BIT(9)
448 #define THC_M_PRT_ERR_CAUSE_FRAME_BABBLE_ERR BIT(10)
449 #define THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR BIT(12)
450 #define THC_M_PRT_ERR_CAUSE_PRD_ENTRY_ERR BIT(13)
453 #define THC_M_PRT_SW_SEQ_CNTRL_TSSGO BIT(0)
454 #define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CD_IE BIT(1)
457 #define THC_M_PRT_SW_SEQ_STS_TSSDONE BIT(0)
458 #define THC_M_PRT_SW_SEQ_STS_THC_SS_ERR BIT(1)
459 #define THC_M_PRT_SW_SEQ_STS_THC_SS_CIP BIT(3)
466 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_START BIT(0)
467 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_ERROR BIT(1)
468 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC BIT(2)
469 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_DMACPL BIT(3)
470 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_UHS BIT(23)
473 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_CMPL_STATUS BIT(0)
474 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ERROR_STS BIT(1)
475 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_IOC_STS BIT(2)
476 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ACTIVE BIT(3)
483 #define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_BEGINNING_OF_FRAME BIT(29)
484 #define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_END_OF_FRAME BIT(30)
485 #define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_FRAME_TYPE BIT(31)
488 #define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT_RST BIT(31)
491 #define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT_RST BIT(31)
494 #define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT_RST BIT(31)
499 #define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_SEND_ICR_US_EN BIT(15)
505 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_IGNORE BIT(16)
506 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_VAL BIT(17)
507 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_ADDRINC_DIS BIT(24)
508 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_ADDRINC_DIS BIT(25)
509 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_PKT_STRM_EN BIT(26)
510 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_PKT_STRM_EN BIT(27)
511 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_DEVINT_POL BIT(28)
520 #define THC_M_PRT_READ_DMA_CNTRL_START BIT(0)
521 #define THC_M_PRT_READ_DMA_CNTRL_IE_ERROR BIT(1)
522 #define THC_M_PRT_READ_DMA_CNTRL_IE_IOC BIT(2)
523 #define THC_M_PRT_READ_DMA_CNTRL_IE_STALL BIT(3)
524 #define THC_M_PRT_READ_DMA_CNTRL_IE_NDDI BIT(4)
525 #define THC_M_PRT_READ_DMA_CNTRL_IE_EOF BIT(5)
526 #define THC_M_PRT_READ_DMA_CNTRL_IE_DMACPL BIT(7)
529 #define THC_M_PRT_READ_DMA_CNTRL_INT_SW_DMA_EN BIT(28)
530 #define THC_M_PRT_READ_DMA_CNTRL_SOO BIT(29)
531 #define THC_M_PRT_READ_DMA_CNTRL_UHS BIT(30)
532 #define THC_M_PRT_READ_DMA_CNTRL_TPCPR BIT(31)
534 #define THC_M_PRT_READ_DMA_INT_STS_DMACPL_STS BIT(0)
535 #define THC_M_PRT_READ_DMA_INT_STS_ERROR_STS BIT(1)
536 #define THC_M_PRT_READ_DMA_INT_STS_IOC_STS BIT(2)
537 #define THC_M_PRT_READ_DMA_INT_STS_STALL_STS BIT(3)
538 #define THC_M_PRT_READ_DMA_INT_STS_NONDMA_INT_STS BIT(4)
539 #define THC_M_PRT_READ_DMA_INT_STS_EOF_INT_STS BIT(5)
540 #define THC_M_PRT_READ_DMA_INT_STS_ACTIVE BIT(8)
542 #define THC_M_PRT_READ_DMA_ERR_1_DLERR BIT(0)
551 #define THC_M_PRT_TSEQ_CNTRL_1_RGD BIT(2)
552 #define THC_M_PRT_TSEQ_CNTRL_1_EGP BIT(3)
553 #define THC_M_PRT_TSEQ_CNTRL_1_RTO BIT(4)
554 #define THC_M_PRT_TSEQ_CNTRL_1_EWOG BIT(5)
555 #define THC_M_PRT_TSEQ_CNTRL_1_RWOGC BIT(6)
557 #define THC_M_PRT_TSEQ_CNTRL_1_RESET_PREP_CHICKEN BIT(30)
558 #define THC_M_PRT_TSEQ_CNTRL_1_INT_EDG_DET_EN BIT(31)
568 #define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT_RST BIT(31)
571 #define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT_RST BIT(31)
574 #define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT_RST BIT(31)
577 #define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT_RST BIT(31)
580 #define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT_RST BIT(31)
583 #define THC_M_PRT_FRAME_DROP_CNT_1_RFDC BIT(31)
590 #define THC_M_PRT_READ_DMA_ERR_2_DLERR BIT(0)
600 #define THC_M_PRT_TSEQ_CNTRL_2_RGD BIT(2)
601 #define THC_M_PRT_TSEQ_CNTRL_2_EGP BIT(3)
602 #define THC_M_PRT_TSEQ_CNTRL_2_RTO BIT(4)
614 #define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT_RST BIT(31)
617 #define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT_RST BIT(31)
620 #define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT_RST BIT(31)
623 #define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT_RST BIT(31)
626 #define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT_RST BIT(31)
629 #define THC_M_PRT_FRAME_DROP_CNT_2_RFDC BIT(31)
633 #define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_I2C_RW_PIO_EN BIT(23)
636 #define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_RX_DLEN_EN BIT(23)
639 #define THC_M_PRT_PRD_EMPTY_CNT_1_RPTEC BIT(31)
640 #define THC_M_PRT_PRD_EMPTY_CNT_2_RPTEC BIT(31)
645 #define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN BIT(25)
654 #define THC_ARB_POLICY_UFRAME_BOUNDARY 1
659 #define THC_PIO_DONE_TIMEOUT_US USEC_PER_SEC /* 1s */
665 /* Last fragment indicator is bit 15 for HIDSPI */
672 #define THC_BITMASK_INTERRUPT_TYPE_DATA 1
676 #define THC_QUIESCE_EN_TIMEOUT_US USEC_PER_SEC /* 1s */
685 #define THC_LTR_SCALE_1 1
691 #define THC_LTR_MODE_LP 1
692 #define THC_LTR_MIN_VAL_SCALE_3 BIT(10)
693 #define THC_LTR_MAX_VAL_SCALE_3 BIT(15)
694 #define THC_LTR_MIN_VAL_SCALE_4 BIT(15)
695 #define THC_LTR_MAX_VAL_SCALE_4 BIT(20)
696 #define THC_LTR_MIN_VAL_SCALE_5 BIT(20)
697 #define THC_LTR_MAX_VAL_SCALE_5 BIT(25)
721 * @THC_SINGLE_IO: single IO mode, 1(opcode) - 1(address) - 1(data)
722 * @THC_DUAL_IO: dual IO mode, 1(opcode) - 2(address) - 2(data)
723 * @THC_QUAD_IO: quad IO mode, 1(opcode) - 4(address) - 4(data)
724 * @THC_QUAD_PARALLEL_IO: parallel quad IO mode, 4(opcode) - 4(address) - 4(data)
728 THC_DUAL_IO = 1,
736 * This DIV final value is determined by THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN bit.
748 THC_SPI_FRQ_DIV_1 = 1,
757 /* THC I2C sub-system registers */
827 * THC I2C sub-system supported speed mode
830 THC_I2C_STANDARD = 1,
835 /* THC I2C sub-system register bits definition */
836 #define THC_I2C_IC_ENABLE_ENABLE BIT(0)
837 #define THC_I2C_IC_ENABLE_ABORT BIT(1)
838 #define THC_I2C_IC_ENABLE_TX_CMD_BLOCK BIT(2)
839 #define THC_I2C_IC_ENABLE_SDA_STUCK_RECOVERY_ENABLE BIT(3)
840 #define THC_I2C_IC_ENABLE_SMBUS_CLK_RESET BIT(16)
841 #define THC_I2C_IC_ENABLE_SMBUS_SUSPEND_EN BIT(17)
842 #define THC_I2C_IC_ENABLE_SMBUS_ALERT_EN BIT(18)
844 #define THC_I2C_IC_CON_MASTER_MODE BIT(0)
845 #define THC_I2C_IC_CON_SPEED GENMASK(2, 1)
846 #define THC_I2C_IC_CON_IC_10BITADDR_SLAVE BIT(3)
847 #define THC_I2C_IC_CON_IC_10BITADDR_MASTER BIT(4)
848 #define THC_I2C_IC_CON_IC_RESTART_EN BIT(5)
849 #define THC_I2C_IC_CON_IC_SLAVE_DISABLE BIT(6)
850 #define THC_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
851 #define THC_I2C_IC_CON_TX_EMPTY_CTRL BIT(8)
852 #define THC_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
853 #define THC_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE BIT(10)
854 #define THC_I2C_IC_CON_BUS_CLEAR_FEATURE_CTRL BIT(11)
855 #define THC_I2C_IC_CON_OPTIONAL_SAR_CTRL BIT(16)
856 #define THC_I2C_IC_CON_SMBUS_SLAVE_QUICK_EN BIT(17)
857 #define THC_I2C_IC_CON_SMBUS_ARP_EN BIT(18)
858 #define THC_I2C_IC_CON_SMBUS_PERSISTENT_SLV_ADDR_EN BIT(19)
861 #define THC_I2C_IC_TAR_GC_OR_START BIT(10)
862 #define THC_I2C_IC_TAR_SPECIAL BIT(11)
863 #define THC_I2C_IC_TAR_IC_10BITADDR_MASTER BIT(12)
864 #define THC_I2C_IC_TAR_DEVICE_ID BIT(13)
865 #define THC_I2C_IC_TAR_SMBUS_QUICK_CMD BIT(16)
867 #define THC_I2C_IC_INTR_MASK_M_RX_UNDER BIT(0)
868 #define THC_I2C_IC_INTR_MASK_M_RX_OVER BIT(1)
869 #define THC_I2C_IC_INTR_MASK_M_RX_FULL BIT(2)
870 #define THC_I2C_IC_INTR_MASK_M_TX_OVER BIT(3)
871 #define THC_I2C_IC_INTR_MASK_M_TX_EMPTY BIT(4)
872 #define THC_I2C_IC_INTR_MASK_M_RD_REQ BIT(5)
873 #define THC_I2C_IC_INTR_MASK_M_TX_ABRT BIT(6)
874 #define THC_I2C_IC_INTR_MASK_M_RX_DONE BIT(7)
875 #define THC_I2C_IC_INTR_MASK_M_ACTIVITY BIT(8)
876 #define THC_I2C_IC_INTR_MASK_M_STOP_DET BIT(9)
877 #define THC_I2C_IC_INTR_MASK_M_START_DET BIT(10)
878 #define THC_I2C_IC_INTR_MASK_M_GEN_CALL BIT(11)
879 #define THC_I2C_IC_INTR_MASK_M_RESTART_DET BIT(12)
880 #define THC_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD BIT(13)
881 #define THC_I2C_IC_INTR_MASK_M_SCL_STUCK_AT_LOW BIT(14)
883 #define THC_I2C_IC_DMA_CR_RDMAE BIT(0)
884 #define THC_I2C_IC_DMA_CR_TDMAE BIT(1)