142 	case 0:  in ipu_degrees_to_rot_mode()
143 		vf = hf = r90 = 0;  in ipu_degrees_to_rot_mode()
146 		vf = hf = 0;  in ipu_degrees_to_rot_mode()
151 		r90 = 0;  in ipu_degrees_to_rot_mode()
164 	return 0;  in ipu_degrees_to_rot_mode()
218 #define idma_mask(ch)			(1 << ((ch) & 0x1f))
224  * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
266 	{ .chnum =  5, .reg = IDMAC_CH_LOCK_EN_1, .shift =  0, },
277 	{ .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift =  0, },
293 	case 0:  in ipu_idmac_lock_enable()
295 		bursts = 0x00; /* locking disabled */  in ipu_idmac_lock_enable()
298 		bursts = 0x01;  in ipu_idmac_lock_enable()
301 		bursts = 0x02;  in ipu_idmac_lock_enable()
304 		bursts = 0x03;  in ipu_idmac_lock_enable()
318 	for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {  in ipu_idmac_lock_enable()
328 	regval &= ~(0x03 << idmac_lock_en_info[i].shift);  in ipu_idmac_lock_enable()
334 	return 0;  in ipu_idmac_lock_enable()
360 	return 0;  in ipu_module_enable()
386 	return 0;  in ipu_module_disable()
395 	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;  in ipu_idmac_get_current_buffer()
403 	u32 reg = 0;  in ipu_idmac_buffer_is_ready()
407 	case 0:  in ipu_idmac_buffer_is_ready()
419 	return ((reg & idma_mask(channel->num)) != 0);  in ipu_idmac_buffer_is_ready()
432 	if (buf_num == 0)  in ipu_idmac_select_buffer()
449 	ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */  in ipu_idmac_clear_buffer()
451 	case 0:  in ipu_idmac_clear_buffer()
463 	ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */  in ipu_idmac_clear_buffer()
483 	return 0;  in ipu_idmac_enable_channel()
500 	return 0;  in ipu_idmac_wait_busy()
520 	ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */  in ipu_idmac_disable_channel()
534 	ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */  in ipu_idmac_disable_channel()
543 	return 0;  in ipu_idmac_disable_channel()
576 	ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);  in ipu_memory_reset()
579 	while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {  in ipu_memory_reset()
585 	return 0;  in ipu_memory_reset()
672 		.src =  { IPUV3_CHANNEL_CSI_DIRECT, 0 },
682 	for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {  in find_fsu_link_info()
721 	return 0;  in ipu_fsu_link()
753 	return 0;  in ipu_fsu_unlink()
789 	.cm_ofs = 0x1e000000,
790 	.cpmem_ofs = 0x1f000000,
791 	.srm_ofs = 0x1f040000,
792 	.tpm_ofs = 0x1f060000,
793 	.csi0_ofs = 0x1e030000,
794 	.csi1_ofs = 0x1e038000,
795 	.ic_ofs = 0x1e020000,
796 	.disp0_ofs = 0x1e040000,
797 	.disp1_ofs = 0x1e048000,
798 	.dc_tmpl_ofs = 0x1f080000,
799 	.vdi_ofs = 0x1e068000,
805 	.cm_ofs = 0x06000000,
806 	.cpmem_ofs = 0x07000000,
807 	.srm_ofs = 0x07040000,
808 	.tpm_ofs = 0x07060000,
809 	.csi0_ofs = 0x06030000,
810 	.csi1_ofs = 0x06038000,
811 	.ic_ofs = 0x06020000,
812 	.disp0_ofs = 0x06040000,
813 	.disp1_ofs = 0x06048000,
814 	.dc_tmpl_ofs = 0x07080000,
815 	.vdi_ofs = 0x06068000,
821 	.cm_ofs = 0x00200000,
822 	.cpmem_ofs = 0x00300000,
823 	.srm_ofs = 0x00340000,
824 	.tpm_ofs = 0x00360000,
825 	.csi0_ofs = 0x00230000,
826 	.csi1_ofs = 0x00238000,
827 	.ic_ofs = 0x00220000,
828 	.disp0_ofs = 0x00240000,
829 	.disp1_ofs = 0x00248000,
830 	.dc_tmpl_ofs = 0x00380000,
831 	.vdi_ofs = 0x00268000,
859 	ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,  in ipu_submodules_init()
895 	ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,  in ipu_submodules_init()
936 	return 0;  in ipu_submodules_init()
947 	ipu_di_exit(ipu, 0);  in ipu_submodules_init()
957 	ipu_csi_exit(ipu, 0);  in ipu_submodules_init()
970 	for (i = 0; i < num_regs; i++) {  in ipu_irq_handle()
985 	static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};  in ipu_irq_handler()
1033 	ipu_di_exit(ipu, 0);  in ipu_submodules_exit()
1038 	ipu_csi_exit(ipu, 0);  in ipu_submodules_exit()
1048 	return 0;  in platform_remove_devices_fn()
1065 			.csi = 0,
1066 			.dma[0] = IPUV3_CHANNEL_CSI0,
1073 			.dma[0] = IPUV3_CHANNEL_CSI1,
1079 			.di = 0,
1082 			.dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1091 			.dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1112 	for (i = 0; i < ARRAY_SIZE(client_reg); i++) {  in ipu_add_client_devices()
1147 	return 0;  in ipu_add_client_devices()
1161 		0x400100d0, 0xffe000fd,  in ipu_irq_init()
1162 		0x400100d0, 0xffe000fd,  in ipu_irq_init()
1163 		0x400100d0, 0xffe000fd,  in ipu_irq_init()
1164 		0x4077ffff, 0xffe7e1fd,  in ipu_irq_init()
1165 		0x23fffffe, 0x8880fff0,  in ipu_irq_init()
1166 		0xf98fe7d0, 0xfff81fff,  in ipu_irq_init()
1167 		0x400100d0, 0xffe000fd,  in ipu_irq_init()
1168 		0x00000000,  in ipu_irq_init()
1180 					     handle_level_irq, 0, 0, 0);  in ipu_irq_init()
1181 	if (ret < 0) {  in ipu_irq_init()
1188 	for (i = 0; i < IPU_NUM_IRQS; i += 32) {  in ipu_irq_init()
1189 		ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));  in ipu_irq_init()
1193 	for (i = 0; i < IPU_NUM_IRQS; i += 32) {  in ipu_irq_init()
1209 	return 0;  in ipu_irq_init()
1221 	for (i = 0; i < IPU_NUM_IRQS; i++) {  in ipu_irq_exit()
1239 		ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));  in ipu_dump()
1243 		ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));  in ipu_dump()
1247 		ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));  in ipu_dump()
1251 		ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));  in ipu_dump()
1262 	for (i = 0; i < 15; i++)  in ipu_dump()
1281 	irq_sync = platform_get_irq(pdev, 0);  in ipu_probe()
1283 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in ipu_probe()
1288 	if (!res || irq_sync < 0 || irq_err < 0)  in ipu_probe()
1298 	if (ipu->id < 0)  in ipu_probe()
1299 		ipu->id = 0;  in ipu_probe()
1316 	dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",  in ipu_probe()
1318 	dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",  in ipu_probe()
1320 	dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",  in ipu_probe()
1322 	dev_dbg(&pdev->dev, "csi0:    0x%08lx\n",  in ipu_probe()
1324 	dev_dbg(&pdev->dev, "csi1:    0x%08lx\n",  in ipu_probe()
1326 	dev_dbg(&pdev->dev, "ic:      0x%08lx\n",  in ipu_probe()
1328 	dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",  in ipu_probe()
1330 	dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",  in ipu_probe()
1332 	dev_dbg(&pdev->dev, "srm:      0x%08lx\n",  in ipu_probe()
1334 	dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",  in ipu_probe()
1336 	dev_dbg(&pdev->dev, "dc:       0x%08lx\n",  in ipu_probe()
1338 	dev_dbg(&pdev->dev, "ic:       0x%08lx\n",  in ipu_probe()
1340 	dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",  in ipu_probe()
1342 	dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",  in ipu_probe()
1387 	ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),  in ipu_probe()
1403 	return 0;  in ipu_probe()