1 // SPDX-License-Identifier: GPL-2.0-only
6  * Copyright (C) 2011-2017 NVIDIA Corporation
14 static void host1x_debug_show_channel_cdma(struct host1x *host,  in host1x_debug_show_channel_cdma()  argument
18 	struct host1x_cdma *cdma = &ch->cdma;  in host1x_debug_show_channel_cdma()
43 	host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));  in host1x_debug_show_channel_cdma()
46 	    !ch->cdma.push_buffer.mapped) {  in host1x_debug_show_channel_cdma()
66 static void host1x_debug_show_channel_fifo(struct host1x *host,  in host1x_debug_show_channel_fifo()  argument
77 	host1x_debug_output(o, "%u: fifo:\n", ch->id);  in host1x_debug_show_channel_fifo()
91 	host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);  in host1x_debug_show_channel_fifo()
95 	val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);  in host1x_debug_show_channel_fifo()
96 	host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL);  in host1x_debug_show_channel_fifo()
98 	val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS);  in host1x_debug_show_channel_fifo()
102 	val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));  in host1x_debug_show_channel_fifo()
109 		val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);  in host1x_debug_show_channel_fifo()
111 		host1x_hypervisor_writel(host, val,  in host1x_debug_show_channel_fifo()
114 		val = host1x_hypervisor_readl(host,  in host1x_debug_show_channel_fifo()
119 					    rd_ptr - start, val);  in host1x_debug_show_channel_fifo()
124 			data_count--;  in host1x_debug_show_channel_fifo()
137 	host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);  in host1x_debug_show_channel_fifo()
138 	host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);  in host1x_debug_show_channel_fifo()
142 static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)  in host1x_debug_show_mlocks()  argument