Lines Matching +full:tegra210 +full:- +full:vi
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
27 #include <asm/dma-iommu.h>
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
57 return readl(host1x->hv_regs + r); in host1x_hypervisor_readl()
62 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_writel()
69 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_readl()
76 writel(v, ch->regs + r); in host1x_ch_writel()
81 return readl(ch->regs + r); in host1x_ch_readl()
156 { /* VI 0 */ .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 },
157 { /* VI 1 */ .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 },
158 { /* VI 2 */ .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 },
159 { /* VI 3 */ .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 },
160 { /* VI 4 */ .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 },
161 { /* VI 5 */ .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 },
162 { /* VI 6 */ .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 },
163 { /* VI 7 */ .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 },
164 { /* VI 8 */ .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 },
165 { /* VI 9 */ .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 },
166 { /* VI 10 */ .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 },
167 { /* VI 11 */ .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },
198 { /* VI */ .base = 0x1b80, .offset = 0x800, .limit = 0x800 },
249 { /* VI MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 },
282 { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
283 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
284 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
285 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
286 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
287 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
288 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
289 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
296 const struct host1x_info *info = host->info; in host1x_setup_virtualization_tables()
299 if (!info->has_hypervisor) in host1x_setup_virtualization_tables()
302 for (i = 0; i < info->num_sid_entries; i++) { in host1x_setup_virtualization_tables()
303 const struct host1x_sid_entry *entry = &info->sid_table[i]; in host1x_setup_virtualization_tables()
305 host1x_hypervisor_writel(host, entry->offset, entry->base); in host1x_setup_virtualization_tables()
306 host1x_hypervisor_writel(host, entry->limit, entry->base + 4); in host1x_setup_virtualization_tables()
309 for (i = 0; i < info->streamid_vm_table.count; i++) { in host1x_setup_virtualization_tables()
311 host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i); in host1x_setup_virtualization_tables()
314 for (i = 0; i < info->classid_vm_table.count; i++) { in host1x_setup_virtualization_tables()
316 host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i); in host1x_setup_virtualization_tables()
319 for (i = 0; i < info->mmio_vm_table.count; i++) { in host1x_setup_virtualization_tables()
321 host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i); in host1x_setup_virtualization_tables()
340 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can in host1x_wants_iommu()
348 * buffers will be mapped into a 32-bit IOVA space that host1x can in host1x_wants_iommu()
356 if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) { in host1x_wants_iommu()
366 struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev); in host1x_iommu_attach()
370 if (host->dev->archdata.mapping) { in host1x_iommu_attach()
372 to_dma_iommu_mapping(host->dev); in host1x_iommu_attach()
373 arm_iommu_detach_device(host->dev); in host1x_iommu_attach()
376 domain = iommu_get_domain_for_dev(host->dev); in host1x_iommu_attach()
391 host->group = iommu_group_get(host->dev); in host1x_iommu_attach()
392 if (host->group) { in host1x_iommu_attach()
401 host->domain = iommu_paging_domain_alloc(host->dev); in host1x_iommu_attach()
402 if (IS_ERR(host->domain)) { in host1x_iommu_attach()
403 err = PTR_ERR(host->domain); in host1x_iommu_attach()
404 host->domain = NULL; in host1x_iommu_attach()
408 err = iommu_attach_group(host->domain, host->group); in host1x_iommu_attach()
410 if (err == -ENODEV) in host1x_iommu_attach()
416 geometry = &host->domain->geometry; in host1x_iommu_attach()
417 start = geometry->aperture_start & host->info->dma_mask; in host1x_iommu_attach()
418 end = geometry->aperture_end & host->info->dma_mask; in host1x_iommu_attach()
420 order = __ffs(host->domain->pgsize_bitmap); in host1x_iommu_attach()
421 init_iova_domain(&host->iova, 1UL << order, start >> order); in host1x_iommu_attach()
422 host->iova_end = end; in host1x_iommu_attach()
424 domain = host->domain; in host1x_iommu_attach()
430 iommu_domain_free(host->domain); in host1x_iommu_attach()
431 host->domain = NULL; in host1x_iommu_attach()
435 iommu_group_put(host->group); in host1x_iommu_attach()
436 host->group = NULL; in host1x_iommu_attach()
443 u64 mask = host->info->dma_mask; in host1x_iommu_init()
450 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err); in host1x_iommu_init()
462 if (!domain && !host->info->has_wide_gather) in host1x_iommu_init()
465 err = dma_coerce_mask_and_coherent(host->dev, mask); in host1x_iommu_init()
467 dev_err(host->dev, "failed to set DMA mask: %d\n", err); in host1x_iommu_init()
476 if (host->domain) { in host1x_iommu_exit()
477 put_iova_domain(&host->iova); in host1x_iommu_exit()
478 iommu_detach_group(host->domain, host->group); in host1x_iommu_exit()
480 iommu_domain_free(host->domain); in host1x_iommu_exit()
481 host->domain = NULL; in host1x_iommu_exit()
485 iommu_group_put(host->group); in host1x_iommu_exit()
486 host->group = NULL; in host1x_iommu_exit()
494 host->resets[0].id = "mc"; in host1x_get_resets()
495 host->resets[1].id = "host1x"; in host1x_get_resets()
496 host->nresets = ARRAY_SIZE(host->resets); in host1x_get_resets()
499 host->dev, host->nresets, host->resets); in host1x_get_resets()
501 dev_err(host->dev, "failed to get reset: %d\n", err); in host1x_get_resets()
513 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); in host1x_probe()
515 return -ENOMEM; in host1x_probe()
517 host->info = of_device_get_match_data(&pdev->dev); in host1x_probe()
519 if (host->info->has_hypervisor) { in host1x_probe()
520 host->regs = devm_platform_ioremap_resource_byname(pdev, "vm"); in host1x_probe()
521 if (IS_ERR(host->regs)) in host1x_probe()
522 return PTR_ERR(host->regs); in host1x_probe()
524 host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); in host1x_probe()
525 if (IS_ERR(host->hv_regs)) in host1x_probe()
526 return PTR_ERR(host->hv_regs); in host1x_probe()
528 if (host->info->has_common) { in host1x_probe()
529 host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common"); in host1x_probe()
530 if (IS_ERR(host->common_regs)) in host1x_probe()
531 return PTR_ERR(host->common_regs); in host1x_probe()
534 host->regs = devm_platform_ioremap_resource(pdev, 0); in host1x_probe()
535 if (IS_ERR(host->regs)) in host1x_probe()
536 return PTR_ERR(host->regs); in host1x_probe()
539 for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) { in host1x_probe()
545 if (err == -ENXIO) in host1x_probe()
550 host->syncpt_irqs[i] = err; in host1x_probe()
553 host->num_syncpt_irqs = i; in host1x_probe()
557 host->syncpt_irqs[0] = platform_get_irq(pdev, 0); in host1x_probe()
558 if (host->syncpt_irqs[0] < 0) in host1x_probe()
559 return host->syncpt_irqs[0]; in host1x_probe()
561 host->num_syncpt_irqs = 1; in host1x_probe()
564 mutex_init(&host->devices_lock); in host1x_probe()
565 INIT_LIST_HEAD(&host->devices); in host1x_probe()
566 INIT_LIST_HEAD(&host->list); in host1x_probe()
567 host->dev = &pdev->dev; in host1x_probe()
572 host->dev->dma_parms = &host->dma_parms; in host1x_probe()
573 dma_set_max_seg_size(host->dev, UINT_MAX); in host1x_probe()
575 if (host->info->init) { in host1x_probe()
576 err = host->info->init(host); in host1x_probe()
581 host->clk = devm_clk_get(&pdev->dev, NULL); in host1x_probe()
582 if (IS_ERR(host->clk)) { in host1x_probe()
583 err = PTR_ERR(host->clk); in host1x_probe()
585 if (err != -EPROBE_DEFER) in host1x_probe()
586 dev_err(&pdev->dev, "failed to get clock: %d\n", err); in host1x_probe()
595 host1x_bo_cache_init(&host->cache); in host1x_probe()
599 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err); in host1x_probe()
603 err = host1x_channel_list_init(&host->channel_list, in host1x_probe()
604 host->info->nb_channels); in host1x_probe()
606 dev_err(&pdev->dev, "failed to initialize channel list\n"); in host1x_probe()
612 dev_err(&pdev->dev, "failed to initialize context list\n"); in host1x_probe()
618 dev_err(&pdev->dev, "failed to initialize syncpts\n"); in host1x_probe()
622 mutex_init(&host->intr_mutex); in host1x_probe()
624 pm_runtime_enable(&pdev->dev); in host1x_probe()
626 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); in host1x_probe()
631 err = pm_runtime_resume_and_get(&pdev->dev); in host1x_probe()
637 dev_err(&pdev->dev, "failed to initialize interrupts\n"); in host1x_probe()
647 err = devm_of_platform_populate(&pdev->dev); in host1x_probe()
659 pm_runtime_put_sync_suspend(&pdev->dev); in host1x_probe()
661 pm_runtime_disable(&pdev->dev); in host1x_probe()
664 host1x_memory_context_list_free(&host->context_list); in host1x_probe()
666 host1x_channel_list_free(&host->channel_list); in host1x_probe()
670 host1x_bo_cache_destroy(&host->cache); in host1x_probe()
682 pm_runtime_force_suspend(&pdev->dev); in host1x_remove()
686 host1x_memory_context_list_free(&host->context_list); in host1x_remove()
687 host1x_channel_list_free(&host->channel_list); in host1x_remove()
689 host1x_bo_cache_destroy(&host->cache); in host1x_remove()
701 if (!host->info->skip_reset_assert) { in host1x_runtime_suspend()
702 err = reset_control_bulk_assert(host->nresets, host->resets); in host1x_runtime_suspend()
711 clk_disable_unprepare(host->clk); in host1x_runtime_suspend()
712 reset_control_bulk_release(host->nresets, host->resets); in host1x_runtime_suspend()
729 err = reset_control_bulk_acquire(host->nresets, host->resets); in host1x_runtime_resume()
735 err = clk_prepare_enable(host->clk); in host1x_runtime_resume()
741 err = reset_control_bulk_deassert(host->nresets, host->resets); in host1x_runtime_resume()
754 clk_disable_unprepare(host->clk); in host1x_runtime_resume()
756 reset_control_bulk_release(host->nresets, host->resets); in host1x_runtime_resume()
769 .name = "tegra-host1x",
806 * host1x_get_dma_mask() - query the supported DMA mask for host1x
814 return host1x->info->dma_mask; in host1x_get_dma_mask()
818 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");