90 	.sync_offset = 0x3000,
94 	.num_sid_entries = 0,
105 	.sync_offset = 0x3000,
109 	.num_sid_entries = 0,
120 	.sync_offset = 0x2100,
124 	.num_sid_entries = 0,
135 	.sync_offset = 0x2100,
139 	.num_sid_entries = 0,
145 	{ /* SE1      */  .base = 0x1ac8, .offset = 0x90,    .limit = 0x90    },
146 	{ /* SE2      */  .base = 0x1ad0, .offset = 0x90,    .limit = 0x90    },
147 	{ /* SE3      */  .base = 0x1ad8, .offset = 0x90,    .limit = 0x90    },
148 	{ /* SE4      */  .base = 0x1ae0, .offset = 0x90,    .limit = 0x90    },
149 	{ /* ISP      */  .base = 0x1ae8, .offset = 0x50,    .limit = 0x50    },
150 	{ /* VIC      */  .base = 0x1af0, .offset = 0x30,    .limit = 0x34    },
151 	{ /* NVENC    */  .base = 0x1af8, .offset = 0x30,    .limit = 0x34    },
152 	{ /* NVDEC    */  .base = 0x1b00, .offset = 0x30,    .limit = 0x34    },
153 	{ /* NVJPG    */  .base = 0x1b08, .offset = 0x30,    .limit = 0x34    },
154 	{ /* TSEC     */  .base = 0x1b10, .offset = 0x30,    .limit = 0x34    },
155 	{ /* TSECB    */  .base = 0x1b18, .offset = 0x30,    .limit = 0x34    },
156 	{ /* VI 0     */  .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 },
157 	{ /* VI 1     */  .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 },
158 	{ /* VI 2     */  .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 },
159 	{ /* VI 3     */  .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 },
160 	{ /* VI 4     */  .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 },
161 	{ /* VI 5     */  .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 },
162 	{ /* VI 6     */  .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 },
163 	{ /* VI 7     */  .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 },
164 	{ /* VI 8     */  .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 },
165 	{ /* VI 9     */  .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 },
166 	{ /* VI 10    */  .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 },
167 	{ /* VI 11    */  .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },
176 	.sync_offset = 0x0,
187 	{ /* SE1          */  .base = 0x1ac8, .offset = 0x90,  .limit = 0x90  },
188 	{ /* SE2          */  .base = 0x1ad0, .offset = 0x90,  .limit = 0x90  },
189 	{ /* SE3          */  .base = 0x1ad8, .offset = 0x90,  .limit = 0x90  },
190 	{ /* SE4          */  .base = 0x1ae0, .offset = 0x90,  .limit = 0x90  },
191 	{ /* ISP          */  .base = 0x1ae8, .offset = 0x800, .limit = 0x800 },
192 	{ /* VIC          */  .base = 0x1af0, .offset = 0x30,  .limit = 0x34  },
193 	{ /* NVENC        */  .base = 0x1af8, .offset = 0x30,  .limit = 0x34  },
194 	{ /* NVDEC        */  .base = 0x1b00, .offset = 0x30,  .limit = 0x34  },
195 	{ /* NVJPG        */  .base = 0x1b08, .offset = 0x30,  .limit = 0x34  },
196 	{ /* TSEC         */  .base = 0x1b10, .offset = 0x30,  .limit = 0x34  },
197 	{ /* TSECB        */  .base = 0x1b18, .offset = 0x30,  .limit = 0x34  },
198 	{ /* VI           */  .base = 0x1b80, .offset = 0x800, .limit = 0x800 },
199 	{ /* VI_THI       */  .base = 0x1b88, .offset = 0x30,  .limit = 0x34  },
200 	{ /* ISP_THI      */  .base = 0x1b90, .offset = 0x30,  .limit = 0x34  },
201 	{ /* PVA0_CLUSTER */  .base = 0x1b98, .offset = 0x0,   .limit = 0x0   },
202 	{ /* PVA0_CLUSTER */  .base = 0x1ba0, .offset = 0x0,   .limit = 0x0   },
203 	{ /* NVDLA0       */  .base = 0x1ba8, .offset = 0x30,  .limit = 0x34  },
204 	{ /* NVDLA1       */  .base = 0x1bb0, .offset = 0x30,  .limit = 0x34  },
205 	{ /* NVENC1       */  .base = 0x1bb8, .offset = 0x30,  .limit = 0x34  },
206 	{ /* NVDEC1       */  .base = 0x1bc0, .offset = 0x30,  .limit = 0x34  },
213 	.nb_bases = 0,
215 	.sync_offset = 0x0,
231 	{ /* SE1 MMIO     */  .base = 0x1650, .offset = 0x90,  .limit = 0x90  },
232 	{ /* SE1 ch       */  .base = 0x1730, .offset = 0x90,  .limit = 0x90  },
233 	{ /* SE2 MMIO     */  .base = 0x1658, .offset = 0x90,  .limit = 0x90  },
234 	{ /* SE2 ch       */  .base = 0x1738, .offset = 0x90,  .limit = 0x90  },
235 	{ /* SE4 MMIO     */  .base = 0x1660, .offset = 0x90,  .limit = 0x90  },
236 	{ /* SE4 ch       */  .base = 0x1740, .offset = 0x90,  .limit = 0x90  },
237 	{ /* ISP MMIO     */  .base = 0x1680, .offset = 0x800, .limit = 0x800 },
238 	{ /* VIC MMIO     */  .base = 0x1688, .offset = 0x34,  .limit = 0x34  },
239 	{ /* VIC ch       */  .base = 0x17b8, .offset = 0x30,  .limit = 0x30  },
240 	{ /* NVENC MMIO   */  .base = 0x1690, .offset = 0x34,  .limit = 0x34  },
241 	{ /* NVENC ch     */  .base = 0x17c0, .offset = 0x30,  .limit = 0x30  },
242 	{ /* NVDEC MMIO   */  .base = 0x1698, .offset = 0x34,  .limit = 0x34  },
243 	{ /* NVDEC ch     */  .base = 0x17c8, .offset = 0x30,  .limit = 0x30  },
244 	{ /* NVJPG MMIO   */  .base = 0x16a0, .offset = 0x34,  .limit = 0x34  },
245 	{ /* NVJPG ch     */  .base = 0x17d0, .offset = 0x30,  .limit = 0x30  },
246 	{ /* TSEC MMIO    */  .base = 0x16a8, .offset = 0x30,  .limit = 0x34  },
247 	{ /* NVJPG1 MMIO  */  .base = 0x16b0, .offset = 0x34,  .limit = 0x34  },
248 	{ /* NVJPG1 ch    */  .base = 0x17a8, .offset = 0x30,  .limit = 0x30  },
249 	{ /* VI MMIO      */  .base = 0x16b8, .offset = 0x800, .limit = 0x800 },
250 	{ /* VI_THI MMIO  */  .base = 0x16c0, .offset = 0x30,  .limit = 0x34  },
251 	{ /* ISP_THI MMIO */  .base = 0x16c8, .offset = 0x30,  .limit = 0x34  },
252 	{ /* NVDLA MMIO   */  .base = 0x16d8, .offset = 0x30,  .limit = 0x34  },
253 	{ /* NVDLA ch     */  .base = 0x17e0, .offset = 0x30,  .limit = 0x34  },
254 	{ /* NVDLA1 MMIO  */  .base = 0x16e0, .offset = 0x30,  .limit = 0x34  },
255 	{ /* NVDLA1 ch    */  .base = 0x17e8, .offset = 0x30,  .limit = 0x34  },
256 	{ /* OFA MMIO     */  .base = 0x16e8, .offset = 0x34,  .limit = 0x34  },
257 	{ /* OFA ch       */  .base = 0x1768, .offset = 0x30,  .limit = 0x30  },
258 	{ /* VI2 MMIO     */  .base = 0x16f0, .offset = 0x800, .limit = 0x800 },
259 	{ /* VI2_THI MMIO */  .base = 0x16f8, .offset = 0x30,  .limit = 0x34  },
266 	.nb_bases = 0,
268 	.sync_offset = 0x0,
275 	.streamid_vm_table = { 0x1004, 128 },
276 	.classid_vm_table = { 0x1404, 25 },
277 	.mmio_vm_table = { 0x1504, 25 },
302 	for (i = 0; i < info->num_sid_entries; i++) {  in host1x_setup_virtualization_tables()
309 	for (i = 0; i < info->streamid_vm_table.count; i++) {  in host1x_setup_virtualization_tables()
311 		host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);  in host1x_setup_virtualization_tables()
314 	for (i = 0; i < info->classid_vm_table.count; i++) {  in host1x_setup_virtualization_tables()
316 		host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);  in host1x_setup_virtualization_tables()
319 	for (i = 0; i < info->mmio_vm_table.count; i++) {  in host1x_setup_virtualization_tables()
321 		host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);  in host1x_setup_virtualization_tables()
404 		if (err < 0)  in host1x_iommu_attach()
417 				err = 0;  in host1x_iommu_attach()
472 	if (err < 0) {  in host1x_iommu_init()
477 	return 0;  in host1x_iommu_init()
500 	host->resets[0].id = "mc";  in host1x_get_resets()
511 	return 0;  in host1x_get_resets()
540 		host->regs = devm_platform_ioremap_resource(pdev, 0);  in host1x_probe()
545 	for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) {  in host1x_probe()
553 		if (err < 0)  in host1x_probe()
562 	if (i == 0) {  in host1x_probe()
563 		host->syncpt_irqs[0] = platform_get_irq(pdev, 0);  in host1x_probe()
564 		if (host->syncpt_irqs[0] < 0)  in host1x_probe()
565 			return host->syncpt_irqs[0];  in host1x_probe()
604 	if (err < 0) {  in host1x_probe()
650 	if (err < 0)  in host1x_probe()
654 	if (err < 0)  in host1x_probe()
657 	return 0;  in host1x_probe()
720 	return 0;  in host1x_runtime_suspend()
748 	if (err < 0) {  in host1x_runtime_resume()
757 	return 0;  in host1x_runtime_resume()
793 	if (err < 0)  in tegra_host1x_init()
797 	if (err < 0)  in tegra_host1x_init()