Lines Matching +full:zynqmp +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem - KMS API
5 * Copyright (C) 2017 - 2021 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
47 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub;
50 /* -----------------------------------------------------------------------------
61 if (!new_plane_state->crtc)
64 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
80 struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev);
81 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index];
83 if (!old_state->fb)
88 if (plane->index == ZYNQMP_DPSUB_LAYER_GFX)
89 zynqmp_disp_blend_set_global_alpha(dpsub->disp, false,
90 plane->state->alpha >> 8);
98 struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev);
99 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index];
102 if (!old_state->fb ||
103 old_state->fb->format->format != new_state->fb->format->format)
112 if (old_state->fb)
115 zynqmp_disp_layer_set_format(layer, new_state->fb->format);
120 if (plane->index == ZYNQMP_DPSUB_LAYER_GFX)
121 zynqmp_disp_blend_set_global_alpha(dpsub->disp, true,
122 plane->state->alpha >> 8);
127 * implicitly after DPSUB reset during display mode change. DRM
143 .reset = drm_atomic_helper_plane_reset,
153 for (i = 0; i < ARRAY_SIZE(dpsub->drm->planes); i++) {
154 struct zynqmp_disp_layer *layer = dpsub->layers[i];
155 struct drm_plane *plane = &dpsub->drm->planes[i];
162 return -ENOMEM;
167 ret = drm_universal_plane_init(&dpsub->drm->dev, plane, 0,
185 /* -----------------------------------------------------------------------------
191 return container_of(crtc, struct zynqmp_dpsub_drm, crtc)->dpsub;
198 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
201 pm_runtime_get_sync(dpsub->dev);
203 zynqmp_disp_setup_clock(dpsub->disp, adjusted_mode->clock * 1000);
205 ret = clk_prepare_enable(dpsub->vid_clk);
207 dev_err(dpsub->dev, "failed to enable a pixel clock\n");
208 pm_runtime_put_sync(dpsub->dev);
212 zynqmp_disp_enable(dpsub->disp);
215 vrefresh = (adjusted_mode->clock * 1000) /
216 (adjusted_mode->vtotal * adjusted_mode->htotal);
231 old_plane_state = drm_atomic_get_old_plane_state(state, crtc->primary);
233 zynqmp_dpsub_plane_atomic_disable(crtc->primary, state);
235 zynqmp_disp_disable(dpsub->disp);
239 spin_lock_irq(&crtc->dev->event_lock);
240 if (crtc->state->event) {
241 drm_crtc_send_vblank_event(crtc, crtc->state->event);
242 crtc->state->event = NULL;
244 spin_unlock_irq(&crtc->dev->event_lock);
246 clk_disable_unprepare(dpsub->vid_clk);
247 pm_runtime_put_sync(dpsub->dev);
265 if (crtc->state->event) {
269 event = crtc->state->event;
270 crtc->state->event = NULL;
272 event->pipe = drm_crtc_index(crtc);
276 spin_lock_irq(&crtc->dev->event_lock);
278 spin_unlock_irq(&crtc->dev->event_lock);
294 zynqmp_dp_enable_vblank(dpsub->dp);
303 zynqmp_dp_disable_vblank(dpsub->dp);
310 .reset = drm_atomic_helper_crtc_reset,
319 struct drm_plane *plane = &dpsub->drm->planes[ZYNQMP_DPSUB_LAYER_GFX];
320 struct drm_crtc *crtc = &dpsub->drm->crtc;
323 ret = drm_crtc_init_with_planes(&dpsub->drm->dev, crtc, plane,
338 u32 possible_crtcs = drm_crtc_mask(&dpsub->drm->crtc);
341 for (i = 0; i < ARRAY_SIZE(dpsub->drm->planes); i++)
342 dpsub->drm->planes[i].possible_crtcs = possible_crtcs;
346 * zynqmp_dpsub_drm_handle_vblank - Handle the vblank event
354 drm_crtc_handle_vblank(&dpsub->drm->crtc);
357 /* -----------------------------------------------------------------------------
366 unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
369 args->pitch = ALIGN(pitch, dpsub->dma_align);
385 cmd.pitches[i] = ALIGN(cmd.pitches[i], dpsub->dma_align);
396 /* -----------------------------------------------------------------------------
411 .name = "zynqmp-dpsub",
419 struct drm_encoder *encoder = &dpsub->drm->encoder;
435 encoder->possible_crtcs |= drm_crtc_mask(&dpsub->drm->crtc);
436 drm_simple_encoder_init(&dpsub->drm->dev, encoder, DRM_MODE_ENCODER_NONE);
438 ret = drm_bridge_attach(encoder, dpsub->bridge, NULL,
441 dev_err(dpsub->dev, "failed to attach bridge to encoder\n");
446 connector = drm_bridge_connector_init(&dpsub->drm->dev, encoder);
448 dev_err(dpsub->dev, "failed to created connector\n");
455 dev_err(dpsub->dev, "failed to attach connector to encoder\n");
470 zynqmp_dpsub_release(dpdrm->dpsub);
482 * dpsub->drm will remain NULL, which tells the caller that it must
485 dpdrm = devm_drm_dev_alloc(dpsub->dev, &zynqmp_dpsub_drm_driver,
490 dpdrm->dpsub = dpsub;
491 drm = &dpdrm->dev;
497 dpsub->drm = dpdrm;
504 drm->mode_config.funcs = &zynqmp_dpsub_mode_config_funcs;
505 drm->mode_config.min_width = 0;
506 drm->mode_config.min_height = 0;
507 drm->mode_config.max_width = ZYNQMP_DISP_MAX_WIDTH;
508 drm->mode_config.max_height = ZYNQMP_DISP_MAX_HEIGHT;
520 /* Reset all components and register the DRM device. */
539 struct drm_device *drm = &dpsub->drm->dev;
543 drm_encoder_cleanup(&dpsub->drm->encoder);