Lines Matching +full:audio +full:- +full:bridge
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
47 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
52 * @aud_clk: Audio clock
53 * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
58 * @bridge: The DP encoder bridge
63 * @audio: DP audio data
78 struct drm_bridge *bridge; member
86 struct zynqmp_dpsub_audio *audio; member