Lines Matching refs:xe
27 _resize_bar(struct xe_device *xe, int resno, resource_size_t size)
29 struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
38 drm_info(&xe->drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",
43 drm_info(&xe->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
50 static void resize_vram_bar(struct xe_device *xe)
53 struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
81 drm_info(&xe->drm,
99 drm_info(&xe->drm, "Attempting to resize bar from %lluMiB -> %lluMiB\n",
112 drm_info(&xe->drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");
119 _resize_bar(xe, LMEM_BAR, rebar_size);
139 static int determine_lmem_bar_size(struct xe_device *xe)
141 struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
144 drm_err(&xe->drm, "pci resource is not valid\n");
148 resize_vram_bar(xe);
150 xe->mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);
151 xe->mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);
152 if (!xe->mem.vram.io_size)
155 /* XXX: Need to change when xe link code is ready */
156 xe->mem.vram.dpa_base = 0;
159 xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
166 struct xe_device *xe = gt_to_xe(gt);
170 if (GRAPHICS_VER(xe) >= 20) {
191 xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) -
224 struct xe_device *xe = tile_to_xe(tile);
230 if (IS_SRIOV_VF(xe)) {
235 for_each_tile(t, xe, id)
251 if (unlikely(xe->info.platform == XE_DG1)) {
252 *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
261 if (xe->info.has_flat_ccs) {
277 struct xe_device *xe = arg;
281 if (xe->mem.vram.mapping)
282 iounmap(xe->mem.vram.mapping);
284 xe->mem.vram.mapping = NULL;
286 for_each_tile(tile, xe, id)
292 * @xe: the &xe_device
298 int xe_vram_probe(struct xe_device *xe)
310 if (!IS_DGFX(xe))
314 tile = xe_device_get_root_tile(xe);
319 err = determine_lmem_bar_size(xe);
323 drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
324 &xe->mem.vram.io_size);
326 io_size = xe->mem.vram.io_size;
329 for_each_tile(tile, xe, id) {
335 tile->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
339 drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
343 tile->mem.vram.dpa_base = xe->mem.vram.dpa_base + tile_offset;
345 tile->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
348 drm_info(&xe->drm, "Small BAR device\n");
349 drm_info(&xe->drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,
351 drm_info(&xe->drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile->id,
359 if (total_size > xe->mem.vram.io_size) {
360 drm_info(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
361 &total_size, &xe->mem.vram.io_size);
367 xe->mem.vram.actual_physical_size = total_size;
369 drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
370 &xe->mem.vram.actual_physical_size);
371 drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
374 return devm_add_action_or_reset(xe->drm.dev, vram_fini, xe);