22  * DOC: Multi-tile Design
24  * Different vendors use the term "tile" a bit differently, but in the Intel
25  * world, a 'tile' is pretty close to what most people would think of as being
27  * that's what is referred to as a "multi-tile device."  In such cases, pretty
28  * much all hardware is replicated per-tile, although certain responsibilities
30  * solely by the "root tile."  A multi-tile platform takes care of tying the
32  * are forwarded to the root tile, the per-tile vram is combined into a single
36  * the subset of a GPU/tile that is responsible for implementing graphics
41  * Historically most Intel devices were single-tile devices that contained a
42  * single GT.  PVC is an example of an Intel platform built on a multi-tile
43  * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
49  * differently than multi-tile platforms like PVC where nearly everything is
52  * Per-tile functionality (shared by all GTs within the tile):
68  *    within the complete MMIO space provided by the tile, but at different
79  * xe_tile_alloc - Perform per-tile memory allocation
80  * @tile: Tile to perform allocations for
82  * Allocates various per-tile data structures using DRM-managed allocations.
87 static int xe_tile_alloc(struct xe_tile *tile)  in xe_tile_alloc()  argument
89 	struct drm_device *drm = &tile_to_xe(tile)->drm;  in xe_tile_alloc()
91 	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),  in xe_tile_alloc()
93 	if (!tile->mem.ggtt)  in xe_tile_alloc()
95 	tile->mem.ggtt->tile = tile;  in xe_tile_alloc()
97 	tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL);  in xe_tile_alloc()
98 	if (!tile->mem.vram_mgr)  in xe_tile_alloc()
105  * xe_tile_init_early - Initialize the tile and primary GT
106  * @tile: Tile to initialize
108  * @id: Tile ID
110  * Initializes per-tile resources that don't require any interactions with the
115 int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)  in xe_tile_init_early()  argument
119 	tile->xe = xe;  in xe_tile_init_early()
120 	tile->id = id;  in xe_tile_init_early()
122 	err = xe_tile_alloc(tile);  in xe_tile_init_early()
126 	tile->primary_gt = xe_gt_alloc(tile);  in xe_tile_init_early()
127 	if (IS_ERR(tile->primary_gt))  in xe_tile_init_early()
128 		return PTR_ERR(tile->primary_gt);  in xe_tile_init_early()
130 	xe_pcode_init(tile);  in xe_tile_init_early()
136 static int tile_ttm_mgr_init(struct xe_tile *tile)  in tile_ttm_mgr_init()  argument
138 	struct xe_device *xe = tile_to_xe(tile);  in tile_ttm_mgr_init()
141 	if (tile->mem.vram.usable_size) {  in tile_ttm_mgr_init()
142 		err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr);  in tile_ttm_mgr_init()
145 		xe->info.mem_region_mask |= BIT(tile->id) << 1;  in tile_ttm_mgr_init()
152  * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
153  * @tile: The tile to initialize.
155  * This function prepares the tile to allow memory allocations to VRAM, but is
160  * Note that since this is tile initialization, it should not perform any
165 int xe_tile_init_noalloc(struct xe_tile *tile)  in xe_tile_init_noalloc()  argument
169 	err = tile_ttm_mgr_init(tile);  in xe_tile_init_noalloc()
173 	tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);  in xe_tile_init_noalloc()
174 	if (IS_ERR(tile->mem.kernel_bb_pool))  in xe_tile_init_noalloc()
175 		return PTR_ERR(tile->mem.kernel_bb_pool);  in xe_tile_init_noalloc()
177 	xe_wa_apply_tile_workarounds(tile);  in xe_tile_init_noalloc()
179 	err = xe_tile_sysfs_init(tile);  in xe_tile_init_noalloc()
184 void xe_tile_migrate_wait(struct xe_tile *tile)  in xe_tile_migrate_wait()  argument
186 	xe_migrate_wait(tile->migrate);  in xe_tile_migrate_wait()