Lines Matching +full:per +full:- +full:device
1 // SPDX-License-Identifier: MIT
6 #include <linux/fault-inject.h>
22 * DOC: Multi-tile Design
26 * a complete GPU. When multiple GPUs are placed behind a single PCI device,
27 * that's what is referred to as a "multi-tile device." In such cases, pretty
28 * much all hardware is replicated per-tile, although certain responsibilities
30 * solely by the "root tile." A multi-tile platform takes care of tying the
32 * are forwarded to the root tile, the per-tile vram is combined into a single
41 * Historically most Intel devices were single-tile devices that contained a
42 * single GT. PVC is an example of an Intel platform built on a multi-tile
43 * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
47 * single GPU. This is important from a software perspective because multi-GT
49 * differently than multi-tile platforms like PVC where nearly everything is
52 * Per-tile functionality (shared by all GTs within the tile):
53 * - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
55 * - Global GTT
56 * - VRAM (if discrete)
57 * - Interrupt flows
58 * - Migration context
59 * - kernel batchbuffer pool
60 * - Primary GT
61 * - Media GT (if media version >= 13)
63 * Per-GT functionality:
64 * - GuC
65 * - Hardware engines
66 * - Programmable hardware units (subslices, EUs)
67 * - GSI subset of registers (multiple copies of these registers reside
69 * offsets --- 0 for render, 0x380000 for media)
70 * - Multicast register steering
71 * - TLBs to cache page table translations
72 * - Reset capability
73 * - Low-level power management (e.g., C6)
74 * - Clock frequency
75 * - MOCS and PAT programming
79 * xe_tile_alloc - Perform per-tile memory allocation
82 * Allocates various per-tile data structures using DRM-managed allocations.
85 * Returns -ENOMEM if allocations fail, otherwise 0.
89 struct drm_device *drm = &tile_to_xe(tile)->drm; in xe_tile_alloc()
91 tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt), in xe_tile_alloc()
93 if (!tile->mem.ggtt) in xe_tile_alloc()
94 return -ENOMEM; in xe_tile_alloc()
95 tile->mem.ggtt->tile = tile; in xe_tile_alloc()
97 tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL); in xe_tile_alloc()
98 if (!tile->mem.vram_mgr) in xe_tile_alloc()
99 return -ENOMEM; in xe_tile_alloc()
105 * xe_tile_init_early - Initialize the tile and primary GT
107 * @xe: Parent Xe device
110 * Initializes per-tile resources that don't require any interactions with the
119 tile->xe = xe; in xe_tile_init_early()
120 tile->id = id; in xe_tile_init_early()
126 tile->primary_gt = xe_gt_alloc(tile); in xe_tile_init_early()
127 if (IS_ERR(tile->primary_gt)) in xe_tile_init_early()
128 return PTR_ERR(tile->primary_gt); in xe_tile_init_early()
141 if (tile->mem.vram.usable_size) { in tile_ttm_mgr_init()
142 err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr); in tile_ttm_mgr_init()
145 xe->info.mem_region_mask |= BIT(tile->id) << 1; in tile_ttm_mgr_init()
152 * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
161 * GT-specific operations, and thus does not need to hold GT forcewake.
173 tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16); in xe_tile_init_noalloc()
174 if (IS_ERR(tile->mem.kernel_bb_pool)) in xe_tile_init_noalloc()
175 return PTR_ERR(tile->mem.kernel_bb_pool); in xe_tile_init_noalloc()
186 xe_migrate_wait(tile->migrate); in xe_tile_migrate_wait()