Lines Matching +full:multi +full:- +full:bit

1 // SPDX-License-Identifier: MIT
6 #include <linux/fault-inject.h>
23  * DOC: Multi-tile Design
25  * Different vendors use the term "tile" a bit differently, but in the Intel
28  * that's what is referred to as a "multi-tile device."  In such cases, pretty
29  * much all hardware is replicated per-tile, although certain responsibilities
31  * solely by the "root tile."  A multi-tile platform takes care of tying the
33  * are forwarded to the root tile, the per-tile vram is combined into a single
42  * Historically most Intel devices were single-tile devices that contained a
43  * single GT.  PVC is an example of an Intel platform built on a multi-tile
48  * single GPU.  This is important from a software perspective because multi-GT
50  * differently than multi-tile platforms like PVC where nearly everything is
53  * Per-tile functionality (shared by all GTs within the tile):
54  *  - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
56  *  - Global GTT
57  *  - VRAM (if discrete)
58  *  - Interrupt flows
59  *  - Migration context
60  *  - kernel batchbuffer pool
61  *  - Primary GT
62  *  - Media GT (if media version >= 13)
64  * Per-GT functionality:
65  *  - GuC
66  *  - Hardware engines
67  *  - Programmable hardware units (subslices, EUs)
68  *  - GSI subset of registers (multiple copies of these registers reside
70  *    offsets --- 0 for render, 0x380000 for media)
71  *  - Multicast register steering
72  *  - TLBs to cache page table translations
73  *  - Reset capability
74  *  - Low-level power management (e.g., C6)
75  *  - Clock frequency
76  *  - MOCS and PAT programming
80  * xe_tile_alloc - Perform per-tile memory allocation
83  * Allocates various per-tile data structures using DRM-managed allocations.
86  * Returns -ENOMEM if allocations fail, otherwise 0.
90 	struct drm_device *drm = &tile_to_xe(tile)->drm;
92 	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
94 	if (!tile->mem.ggtt)
95 		return -ENOMEM;
96 	tile->mem.ggtt->tile = tile;
102  * xe_tile_init_early - Initialize the tile and primary GT
107  * Initializes per-tile resources that don't require any interactions with the
116 	tile->xe = xe;
117 	tile->id = id;
123 	tile->primary_gt = xe_gt_alloc(tile);
124 	if (IS_ERR(tile->primary_gt))
125 		return PTR_ERR(tile->primary_gt);
138 	if (tile->mem.vram.usable_size) {
139 		err = xe_ttm_vram_mgr_init(tile, &tile->mem.vram.ttm);
142 		xe->info.mem_region_mask |= BIT(tile->id) << 1;
149  * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
158  * GT-specific operations, and thus does not need to hold GT forcewake.
173 	if (xe->info.has_usm && IS_DGFX(xe))
174 		xe_devm_add(tile, &tile->mem.vram);
181 	tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);
182 	if (IS_ERR(tile->mem.kernel_bb_pool))
183 		return PTR_ERR(tile->mem.kernel_bb_pool);
189 	xe_migrate_wait(tile->migrate);