Lines Matching refs:i
25 * pipeline (i.e., CCS engines).
83 static int emit_aux_table_inv(struct xe_hw_engine *hwe, u32 *dw, int i)
90 return emit(gt, dw + i) - dw;
92 return i;
95 static int emit_user_interrupt(u32 *dw, int i)
97 dw[i++] = MI_USER_INTERRUPT;
98 dw[i++] = MI_ARB_ON_OFF | MI_ARB_ENABLE;
99 dw[i++] = MI_ARB_CHECK;
101 return i;
104 static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
106 dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1);
107 dw[i++] = addr;
108 dw[i++] = 0;
109 dw[i++] = value;
111 return i;
114 static int emit_flush_dw(u32 *dw, int i)
116 dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW;
117 dw[i++] = 0;
118 dw[i++] = 0;
119 dw[i++] = 0;
121 return i;
124 static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32 *dw, int i)
126 dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
128 dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
129 dw[i++] = 0;
130 dw[i++] = value;
132 return i;
135 static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
137 dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);
138 dw[i++] = lower_32_bits(batch_addr);
139 dw[i++] = upper_32_bits(batch_addr);
141 return i;
144 static int emit_flush_invalidate(u32 addr, u32 val, u32 flush_flags, u32 *dw, int i)
146 dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW |
149 dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
150 dw[i++] = 0;
151 dw[i++] = val;
153 return i;
157 emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value)
159 dw[i++] = GFX_OP_PIPE_CONTROL(6) | bit_group_0;
160 dw[i++] = bit_group_1;
161 dw[i++] = offset;
162 dw[i++] = 0;
163 dw[i++] = value;
164 dw[i++] = 0;
166 return i;
170 bool invalidate_tlb, u32 *dw, int i)
195 return emit_pipe_control(dw, i, flags0, flags1,
200 u32 *dw, int i)
202 dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1);
203 dw[i++] = lower_32_bits(addr);
204 dw[i++] = upper_32_bits(addr);
205 dw[i++] = lower_32_bits(value);
206 dw[i++] = upper_32_bits(value);
208 return i;
211 static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
219 i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
242 return emit_pipe_control(dw, i, flags0, flags1, 0, 0);
246 bool stall_only, u32 *dw, int i)
258 return emit_pipe_control(dw, i, flags0, flags1, addr, value);
270 u32 *dw, int i)
276 dw[i++] = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT | MI_SRM_ADD_CS_OFFSET;
277 dw[i++] = reg.addr;
278 dw[i++] = xe_lrc_ctx_job_timestamp_ggtt_addr(lrc);
279 dw[i++] = 0;
286 dw[i++] = MI_STORE_REGISTER_MEM | MI_SRM_USE_GGTT |
288 dw[i++] = reg.addr;
289 dw[i++] = xe_lrc_ctx_timestamp_ggtt_addr(lrc);
290 dw[i++] = 0;
293 return i;
296 static int emit_fake_watchdog(struct xe_lrc *lrc, u32 *dw, int i)
303 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) | MI_LRI_LRM_CS_MMIO;
304 dw[i++] = PR_CTR_THRSH(0).addr;
305 dw[i++] = 2; /* small threshold */
306 dw[i++] = PR_CTR_CTRL(0).addr;
307 dw[i++] = CTR_LOGIC_OP(START);
309 dw[i++] = MI_SEMAPHORE_WAIT | MI_SEMW_GGTT | MI_SEMW_POLL | MI_SEMW_COMPARE(SAD_EQ_SDD);
310 dw[i++] = 0xdead; /* this should never be seen */
311 dw[i++] = lower_32_bits(xe_lrc_ggtt_addr(lrc));
312 dw[i++] = upper_32_bits(xe_lrc_ggtt_addr(lrc));
313 dw[i++] = 0; /* unused token */
315 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_LRM_CS_MMIO;
316 dw[i++] = PR_CTR_CTRL(0).addr;
317 dw[i++] = CTR_LOGIC_OP(STOP);
319 return i;
326 u32 dw[MAX_JOB_SIZE_DW], i = 0;
333 i = emit_fake_watchdog(lrc, dw, i);
335 i = emit_copy_timestamp(gt_to_xe(gt), lrc, dw, i);
338 dw[i++] = preparser_disable(true);
339 i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
340 seqno, MI_INVALIDATE_TLB, dw, i);
341 dw[i++] = preparser_disable(false);
343 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
344 seqno, dw, i);
347 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
350 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
353 i = emit_flush_dw(dw, i);
354 i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
356 dw, i);
359 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
361 i = emit_user_interrupt(dw, i);
363 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
365 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
385 u32 dw[MAX_JOB_SIZE_DW], i = 0;
393 i = emit_fake_watchdog(lrc, dw, i);
395 i = emit_copy_timestamp(xe, lrc, dw, i);
397 dw[i++] = preparser_disable(true);
400 i = emit_aux_table_inv(job->q->hwe, dw, i);
403 i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
404 seqno, MI_INVALIDATE_TLB, dw, i);
406 dw[i++] = preparser_disable(false);
409 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
410 seqno, dw, i);
412 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
415 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
418 i = emit_flush_dw(dw, i);
419 i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
421 dw, i);
424 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
426 i = emit_user_interrupt(dw, i);
428 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
430 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
438 u32 dw[MAX_JOB_SIZE_DW], i = 0;
448 i = emit_fake_watchdog(lrc, dw, i);
450 i = emit_copy_timestamp(xe, lrc, dw, i);
457 i = emit_render_cache_flush(job, dw, i);
459 dw[i++] = preparser_disable(true);
466 i = emit_pipe_invalidate(job->q, mask_flags, job->ring_ops_flush_tlb, dw, i);
469 i = emit_aux_table_inv(job->q->hwe, dw, i);
471 dw[i++] = preparser_disable(false);
473 i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
474 seqno, dw, i);
476 i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
479 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
481 i = emit_render_cache_flush(job, dw, i);
484 i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
486 dw, i);
488 i = emit_pipe_imm_ggtt(job->q, xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i);
490 i = emit_user_interrupt(dw, i);
492 xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
494 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
504 u32 dw[MAX_JOB_SIZE_DW], i = 0;
510 i = emit_copy_timestamp(xe, lrc, dw, i);
512 i = emit_store_imm_ggtt(saddr, seqno, dw, i);
514 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */
516 i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i);
518 dw[i++] = preparser_disable(true);
519 i = emit_flush_invalidate(saddr, seqno, job->migrate_flush_flags, dw, i);
520 dw[i++] = preparser_disable(false);
522 i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i);
524 i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno,
526 dw, i);
528 i = emit_user_interrupt(dw, i);
530 xe_gt_assert(job->q->gt, i <= MAX_JOB_SIZE_DW);
532 xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
549 int i;
558 for (i = 0; i < job->q->width; ++i)
559 __emit_job_gen12_simple(job, job->q->lrc[i],
560 job->ptrs[i].batch_addr,
561 &job->ptrs[i].head,
567 int i;
570 for (i = 0; i < job->q->width; ++i)
571 __emit_job_gen12_video(job, job->q->lrc[i],
572 job->ptrs[i].batch_addr,
573 &job->ptrs[i].head,
579 int i;
581 for (i = 0; i < job->q->width; ++i)
582 __emit_job_gen12_render_compute(job, job->q->lrc[i],
583 job->ptrs[i].batch_addr,
584 &job->ptrs[i].head,