32 #define LRC_VALID				BIT_ULL(0)
93  * [5:0]: Number of NOPs or registers to set values to in case of
98  * is used for offsets smaller than 0x200 while the latter is for values bigger
103  * [6:0]: Register offset, without considering the engine base.
114 #define POSTED BIT(0)  in set_offsets()
115 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))  in set_offsets()
117 	(((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \  in set_offsets()
118 	(((x) >> 2) & 0x7f)  in set_offsets()
131 		count = *data & 0x3f;  in set_offsets()
143 			u32 offset = 0;  in set_offsets()
152 			regs[0] = base + (offset << 2);  in set_offsets()
157 	*regs = MI_BATCH_BUFFER_END | BIT(0);  in set_offsets()
163 	REG16(0x244),
164 	REG(0x034),
165 	REG(0x030),
166 	REG(0x038),
167 	REG(0x03c),
168 	REG(0x168),
169 	REG(0x140),
170 	REG(0x110),
171 	REG(0x1c0),
172 	REG(0x1c4),
173 	REG(0x1c8),
174 	REG(0x180),
175 	REG16(0x2b4),
179 	REG16(0x3a8),
180 	REG16(0x28c),
181 	REG16(0x288),
182 	REG16(0x284),
183 	REG16(0x280),
184 	REG16(0x27c),
185 	REG16(0x278),
186 	REG16(0x274),
187 	REG16(0x270),
189 	0
195 	REG16(0x244),
196 	REG(0x034),
197 	REG(0x030),
198 	REG(0x038),
199 	REG(0x03c),
200 	REG(0x168),
201 	REG(0x140),
202 	REG(0x110),
203 	REG(0x1c0),
204 	REG(0x1c4),
205 	REG(0x1c8),
206 	REG(0x180),
207 	REG16(0x2b4),
208 	REG(0x120),
209 	REG(0x124),
213 	REG16(0x3a8),
214 	REG16(0x28c),
215 	REG16(0x288),
216 	REG16(0x284),
217 	REG16(0x280),
218 	REG16(0x27c),
219 	REG16(0x278),
220 	REG16(0x274),
221 	REG16(0x270),
223 	0
229 	REG16(0x244),
230 	REG(0x034),
231 	REG(0x030),
232 	REG(0x038),
233 	REG(0x03c),
234 	REG(0x168),
235 	REG(0x140),
236 	REG(0x110),
237 	REG(0x1c0),
238 	REG(0x1c4),
239 	REG(0x1c8),
240 	REG(0x180),
241 	REG16(0x2b4),
245 	REG16(0x3a8),
246 	REG16(0x28c),
247 	REG16(0x288),
248 	REG16(0x284),
249 	REG16(0x280),
250 	REG16(0x27c),
251 	REG16(0x278),
252 	REG16(0x274),
253 	REG16(0x270),
256 	REG(0x1b0),
257 	REG16(0x5a8),
258 	REG16(0x5ac),
261 	LRI(1, 0),
262 	REG(0x0c8),
266 	REG16(0x588),
267 	REG16(0x588),
268 	REG16(0x588),
269 	REG16(0x588),
270 	REG16(0x588),
271 	REG16(0x588),
272 	REG(0x028),
273 	REG(0x09c),
274 	REG(0x0c0),
275 	REG(0x178),
276 	REG(0x17c),
277 	REG16(0x358),
278 	REG(0x170),
279 	REG(0x150),
280 	REG(0x154),
281 	REG(0x158),
282 	REG16(0x41c),
283 	REG16(0x600),
284 	REG16(0x604),
285 	REG16(0x608),
286 	REG16(0x60c),
287 	REG16(0x610),
288 	REG16(0x614),
289 	REG16(0x618),
290 	REG16(0x61c),
291 	REG16(0x620),
292 	REG16(0x624),
293 	REG16(0x628),
294 	REG16(0x62c),
295 	REG16(0x630),
296 	REG16(0x634),
297 	REG16(0x638),
298 	REG16(0x63c),
299 	REG16(0x640),
300 	REG16(0x644),
301 	REG16(0x648),
302 	REG16(0x64c),
303 	REG16(0x650),
304 	REG16(0x654),
305 	REG16(0x658),
306 	REG16(0x65c),
307 	REG16(0x660),
308 	REG16(0x664),
309 	REG16(0x668),
310 	REG16(0x66c),
311 	REG16(0x670),
312 	REG16(0x674),
313 	REG16(0x678),
314 	REG16(0x67c),
315 	REG(0x068),
316 	REG(0x084),
319 	0
325 	REG16(0x244),
326 	REG(0x034),
327 	REG(0x030),
328 	REG(0x038),
329 	REG(0x03c),
330 	REG(0x168),
331 	REG(0x140),
332 	REG(0x110),
333 	REG(0x1c0),
334 	REG(0x1c4),
335 	REG(0x1c8),
336 	REG(0x180),
337 	REG16(0x2b4),
341 	REG16(0x3a8),
342 	REG16(0x28c),
343 	REG16(0x288),
344 	REG16(0x284),
345 	REG16(0x280),
346 	REG16(0x27c),
347 	REG16(0x278),
348 	REG16(0x274),
349 	REG16(0x270),
352 	REG(0x1b0),
353 	REG16(0x5a8),
354 	REG16(0x5ac),
357 	LRI(1, 0),
358 	REG(0x0c8),
360 	0
366 	REG16(0x244),
367 	REG(0x034),
368 	REG(0x030),
369 	REG(0x038),
370 	REG(0x03c),
371 	REG(0x168),
372 	REG(0x140),
373 	REG(0x110),
374 	REG(0x1c0),
375 	REG(0x1c4),
376 	REG(0x1c8),
377 	REG(0x180),
378 	REG16(0x2b4),
379 	REG(0x120),
380 	REG(0x124),
384 	REG16(0x3a8),
385 	REG16(0x28c),
386 	REG16(0x288),
387 	REG16(0x284),
388 	REG16(0x280),
389 	REG16(0x27c),
390 	REG16(0x278),
391 	REG16(0x274),
392 	REG16(0x270),
395 	REG(0x1b0),
396 	REG16(0x5a8),
397 	REG16(0x5ac),
400 	LRI(1, 0),
401 	REG(0x0c8),
403 	0
409 	REG16(0x244),
410 	REG(0x034),
411 	REG(0x030),
412 	REG(0x038),
413 	REG(0x03c),
414 	REG(0x168),
415 	REG(0x140),
416 	REG(0x110),
417 	REG(0x1c0),
418 	REG(0x1c4),
419 	REG(0x1c8),
420 	REG(0x180),
421 	REG16(0x2b4),
422 	REG(0x120),
423 	REG(0x124),
427 	REG16(0x3a8),
428 	REG16(0x28c),
429 	REG16(0x288),
430 	REG16(0x284),
431 	REG16(0x280),
432 	REG16(0x27c),
433 	REG16(0x278),
434 	REG16(0x274),
435 	REG16(0x270),
439 	REG16(0x5a8),
440 	REG16(0x5ac),
443 	LRI(1, 0),
444 	REG(0x0c8),
446 	0
450 	NOP(1),                 /* [0x00] */ \
451 	LRI(15, POSTED),        /* [0x01] */ \
452 	REG16(0x244),           /* [0x02] CTXT_SR_CTL */ \
453 	REG(0x034),             /* [0x04] RING_BUFFER_HEAD */ \
454 	REG(0x030),             /* [0x06] RING_BUFFER_TAIL */ \
455 	REG(0x038),             /* [0x08] RING_BUFFER_START */ \
456 	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */ \
457 	REG(0x168),             /* [0x0c] BB_ADDR_UDW */ \
458 	REG(0x140),             /* [0x0e] BB_ADDR */ \
459 	REG(0x110),             /* [0x10] BB_STATE */ \
460 	REG(0x1c0),             /* [0x12] BB_PER_CTX_PTR */ \
461 	REG(0x1c4),             /* [0x14] RCS_INDIRECT_CTX */ \
462 	REG(0x1c8),             /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
463 	REG(0x180),             /* [0x18] CCID */ \
464 	REG16(0x2b4),           /* [0x1a] SEMAPHORE_TOKEN */ \
465 	REG(0x120),             /* [0x1c] PRT_BB_STATE */ \
466 	REG(0x124),             /* [0x1e] PRT_BB_STATE_UDW */ \
468 	NOP(1),                 /* [0x20] */ \
469 	LRI(9, POSTED),         /* [0x21] */ \
470 	REG16(0x3a8),           /* [0x22] CTX_TIMESTAMP */ \
471 	REG16(0x3ac),           /* [0x24] CTX_TIMESTAMP_UDW */ \
472 	REG(0x108),             /* [0x26] INDIRECT_RING_STATE */ \
473 	REG16(0x284),           /* [0x28] dummy reg */ \
474 	REG16(0x280),           /* [0x2a] CS_ACC_CTR_THOLD */ \
475 	REG16(0x27c),           /* [0x2c] CS_CTX_SYS_PASID */ \
476 	REG16(0x278),           /* [0x2e] CS_CTX_ASID */ \
477 	REG16(0x274),           /* [0x30] PTBP_UDW */ \
478 	REG16(0x270)            /* [0x32] PTBP_LDW */
483 	NOP(2),                 /* [0x34] */
484 	LRI(2, POSTED),         /* [0x36] */
485 	REG16(0x5a8),           /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */
486 	REG16(0x5ac),           /* [0x39] PREEMPTION_STATUS */
488 	NOP(6),                 /* [0x41] */
489 	LRI(1, 0),              /* [0x47] */
490 	REG(0x0c8),             /* [0x48] R_PWR_CLK_STATE */
492 	0
498 	NOP(4 + 8 + 1),         /* [0x34] */
499 	LRI(2, POSTED),         /* [0x41] */
500 	REG16(0x200),           /* [0x42] BCS_SWCTRL */
501 	REG16(0x204),           /* [0x44] BLIT_CCTL */
503 	0
509 	0
513 	NOP(1),                 /* [0x00] */
514 	LRI(5, POSTED),         /* [0x01] */
515 	REG(0x034),             /* [0x02] RING_BUFFER_HEAD */
516 	REG(0x030),             /* [0x04] RING_BUFFER_TAIL */
517 	REG(0x038),             /* [0x06] RING_BUFFER_START */
518 	REG(0x048),             /* [0x08] RING_BUFFER_START_UDW */
519 	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */
521 	NOP(5),                 /* [0x0c] */
522 	LRI(9, POSTED),         /* [0x11] */
523 	REG(0x168),             /* [0x12] BB_ADDR_UDW */
524 	REG(0x140),             /* [0x14] BB_ADDR */
525 	REG(0x110),             /* [0x16] BB_STATE */
526 	REG16(0x588),           /* [0x18] BB_STACK_WRITE_PORT */
527 	REG16(0x588),           /* [0x20] BB_STACK_WRITE_PORT */
528 	REG16(0x588),           /* [0x22] BB_STACK_WRITE_PORT */
529 	REG16(0x588),           /* [0x24] BB_STACK_WRITE_PORT */
530 	REG16(0x588),           /* [0x26] BB_STACK_WRITE_PORT */
531 	REG16(0x588),           /* [0x28] BB_STACK_WRITE_PORT */
533 	NOP(12),                 /* [0x00] */
535 	0
594 	regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr;  in set_memory_based_intr()
600 	regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr;  in set_memory_based_intr()
602 	regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr;  in set_memory_based_intr()
606 		regs[CTX_CS_INT_VEC_REG] = CS_INT_VEC(0).addr;  in set_memory_based_intr()
616 		return 0x70;  in lrc_ring_mi_mode()
618 		return 0x60;  in lrc_ring_mi_mode()
637 	return 0;  in __xe_lrc_ring_offset()
794 		return 0;  in xe_lrc_indirect_ring_ggtt_addr()
882 #define PVC_CTX_ASID		(0x2e + 1)
883 #define PVC_CTX_ACC_CTR_THOLD	(0x2a + 1)
898 	lrc->flags = 0;  in xe_lrc_init()
918 	lrc->ring.tail = 0;  in xe_lrc_init()
919 	lrc->ctx_timestamp = 0;  in xe_lrc_init()
938 		xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */  in xe_lrc_init()
943 		xe_map_memcpy_to(xe, &map, 0, init_data,  in xe_lrc_init()
969 		xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0);  in xe_lrc_init()
970 		xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0);  in xe_lrc_init()
976 		xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0);  in xe_lrc_init()
982 	xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0);  in xe_lrc_init()
1011 	return 0;  in xe_lrc_init()
1053  * Called when ref == 0, release resources held by the Logical Ring Context
1119 	xe_map_memcpy_to(xe, &ring, 0, data, size);  in __xe_lrc_write_ring()
1233 	    GFXPIPE_SINGLE_DW_CMD(0, 0))  in instr_dw()
1240 	/* Most instructions have the # of dwords (minus 2) in 7:0 */  in instr_dw()
1292 			   dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "",  in dump_mi_command()
1293 			   dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : "");  in dump_mi_command()
1509 	while (remaining_dw > 0) {  in xe_lrc_dump_default()
1591 	int state_table_size = 0;  in xe_lrc_emit_hwe_state_instructions()
1597 	 * setting up the default LRC, the context switch will write 0's  in xe_lrc_emit_hwe_state_instructions()
1624 	for (int i = 0; i < state_table_size; i++) {  in xe_lrc_emit_hwe_state_instructions()
1630 		xe_gt_assert(gt, num_dw != 0);  in xe_lrc_emit_hwe_state_instructions()
1721 	drm_printf(p, "\tHW Context Desc: 0x%08x\n", snapshot->context_desc);  in xe_lrc_snapshot_print()
1722 	drm_printf(p, "\tHW Ring address: 0x%08x\n",  in xe_lrc_snapshot_print()
1724 	drm_printf(p, "\tHW Indirect Ring State: 0x%08x\n",  in xe_lrc_snapshot_print()
1729 	drm_printf(p, "\tRing start: (memory) 0x%08x\n", snapshot->start);  in xe_lrc_snapshot_print()
1732 	drm_printf(p, "\tTimestamp: 0x%08x\n", snapshot->ctx_timestamp);  in xe_lrc_snapshot_print()
1733 	drm_printf(p, "\tJob Timestamp: 0x%08x\n", snapshot->ctx_job_timestamp);  in xe_lrc_snapshot_print()
1738 	drm_printf(p, "\t[HWSP].length: 0x%x\n", LRC_PPHWSP_SIZE);  in xe_lrc_snapshot_print()
1740 	for (i = 0; i < LRC_PPHWSP_SIZE; i += sizeof(u32)) {  in xe_lrc_snapshot_print()
1747 	drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE);  in xe_lrc_snapshot_print()