Lines Matching +full:0 +full:x588
33 #define LRC_VALID BIT_ULL(0)
60 * | Indirect Ring State Page | 0 or 4k, see |
63 * | Indirect Context Page | 0 or 4k, see |
130 * [5:0]: Number of NOPs or registers to set values to in case of
135 * is used for offsets smaller than 0x200 while the latter is for values bigger
140 * [6:0]: Register offset, without considering the engine base.
151 #define POSTED BIT(0) in set_offsets()
152 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
154 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
155 (((x) >> 2) & 0x7f) in set_offsets()
168 count = *data & 0x3f; in set_offsets()
180 u32 offset = 0; in set_offsets()
189 regs[0] = base + (offset << 2); in set_offsets()
194 *regs = MI_BATCH_BUFFER_END | BIT(0); in set_offsets()
200 REG16(0x244),
201 REG(0x034),
202 REG(0x030),
203 REG(0x038),
204 REG(0x03c),
205 REG(0x168),
206 REG(0x140),
207 REG(0x110),
208 REG(0x1c0),
209 REG(0x1c4),
210 REG(0x1c8),
211 REG(0x180),
212 REG16(0x2b4),
216 REG16(0x3a8),
217 REG16(0x28c),
218 REG16(0x288),
219 REG16(0x284),
220 REG16(0x280),
221 REG16(0x27c),
222 REG16(0x278),
223 REG16(0x274),
224 REG16(0x270),
226 0
232 REG16(0x244),
233 REG(0x034),
234 REG(0x030),
235 REG(0x038),
236 REG(0x03c),
237 REG(0x168),
238 REG(0x140),
239 REG(0x110),
240 REG(0x1c0),
241 REG(0x1c4),
242 REG(0x1c8),
243 REG(0x180),
244 REG16(0x2b4),
245 REG(0x120),
246 REG(0x124),
250 REG16(0x3a8),
251 REG16(0x28c),
252 REG16(0x288),
253 REG16(0x284),
254 REG16(0x280),
255 REG16(0x27c),
256 REG16(0x278),
257 REG16(0x274),
258 REG16(0x270),
260 0
266 REG16(0x244),
267 REG(0x034),
268 REG(0x030),
269 REG(0x038),
270 REG(0x03c),
271 REG(0x168),
272 REG(0x140),
273 REG(0x110),
274 REG(0x1c0),
275 REG(0x1c4),
276 REG(0x1c8),
277 REG(0x180),
278 REG16(0x2b4),
282 REG16(0x3a8),
283 REG16(0x28c),
284 REG16(0x288),
285 REG16(0x284),
286 REG16(0x280),
287 REG16(0x27c),
288 REG16(0x278),
289 REG16(0x274),
290 REG16(0x270),
293 REG(0x1b0),
294 REG16(0x5a8),
295 REG16(0x5ac),
298 LRI(1, 0),
299 REG(0x0c8),
303 REG16(0x588),
304 REG16(0x588),
305 REG16(0x588),
306 REG16(0x588),
307 REG16(0x588),
308 REG16(0x588),
309 REG(0x028),
310 REG(0x09c),
311 REG(0x0c0),
312 REG(0x178),
313 REG(0x17c),
314 REG16(0x358),
315 REG(0x170),
316 REG(0x150),
317 REG(0x154),
318 REG(0x158),
319 REG16(0x41c),
320 REG16(0x600),
321 REG16(0x604),
322 REG16(0x608),
323 REG16(0x60c),
324 REG16(0x610),
325 REG16(0x614),
326 REG16(0x618),
327 REG16(0x61c),
328 REG16(0x620),
329 REG16(0x624),
330 REG16(0x628),
331 REG16(0x62c),
332 REG16(0x630),
333 REG16(0x634),
334 REG16(0x638),
335 REG16(0x63c),
336 REG16(0x640),
337 REG16(0x644),
338 REG16(0x648),
339 REG16(0x64c),
340 REG16(0x650),
341 REG16(0x654),
342 REG16(0x658),
343 REG16(0x65c),
344 REG16(0x660),
345 REG16(0x664),
346 REG16(0x668),
347 REG16(0x66c),
348 REG16(0x670),
349 REG16(0x674),
350 REG16(0x678),
351 REG16(0x67c),
352 REG(0x068),
353 REG(0x084),
356 0
362 REG16(0x244),
363 REG(0x034),
364 REG(0x030),
365 REG(0x038),
366 REG(0x03c),
367 REG(0x168),
368 REG(0x140),
369 REG(0x110),
370 REG(0x1c0),
371 REG(0x1c4),
372 REG(0x1c8),
373 REG(0x180),
374 REG16(0x2b4),
378 REG16(0x3a8),
379 REG16(0x28c),
380 REG16(0x288),
381 REG16(0x284),
382 REG16(0x280),
383 REG16(0x27c),
384 REG16(0x278),
385 REG16(0x274),
386 REG16(0x270),
389 REG(0x1b0),
390 REG16(0x5a8),
391 REG16(0x5ac),
394 LRI(1, 0),
395 REG(0x0c8),
397 0
403 REG16(0x244),
404 REG(0x034),
405 REG(0x030),
406 REG(0x038),
407 REG(0x03c),
408 REG(0x168),
409 REG(0x140),
410 REG(0x110),
411 REG(0x1c0),
412 REG(0x1c4),
413 REG(0x1c8),
414 REG(0x180),
415 REG16(0x2b4),
416 REG(0x120),
417 REG(0x124),
421 REG16(0x3a8),
422 REG16(0x28c),
423 REG16(0x288),
424 REG16(0x284),
425 REG16(0x280),
426 REG16(0x27c),
427 REG16(0x278),
428 REG16(0x274),
429 REG16(0x270),
432 REG(0x1b0),
433 REG16(0x5a8),
434 REG16(0x5ac),
437 LRI(1, 0),
438 REG(0x0c8),
440 0
446 REG16(0x244),
447 REG(0x034),
448 REG(0x030),
449 REG(0x038),
450 REG(0x03c),
451 REG(0x168),
452 REG(0x140),
453 REG(0x110),
454 REG(0x1c0),
455 REG(0x1c4),
456 REG(0x1c8),
457 REG(0x180),
458 REG16(0x2b4),
459 REG(0x120),
460 REG(0x124),
464 REG16(0x3a8),
465 REG16(0x28c),
466 REG16(0x288),
467 REG16(0x284),
468 REG16(0x280),
469 REG16(0x27c),
470 REG16(0x278),
471 REG16(0x274),
472 REG16(0x270),
476 REG16(0x5a8),
477 REG16(0x5ac),
480 LRI(1, 0),
481 REG(0x0c8),
483 0
487 NOP(1), /* [0x00] */ \
488 LRI(15, POSTED), /* [0x01] */ \
489 REG16(0x244), /* [0x02] CTXT_SR_CTL */ \
490 REG(0x034), /* [0x04] RING_BUFFER_HEAD */ \
491 REG(0x030), /* [0x06] RING_BUFFER_TAIL */ \
492 REG(0x038), /* [0x08] RING_BUFFER_START */ \
493 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ \
494 REG(0x168), /* [0x0c] BB_ADDR_UDW */ \
495 REG(0x140), /* [0x0e] BB_ADDR */ \
496 REG(0x110), /* [0x10] BB_STATE */ \
497 REG(0x1c0), /* [0x12] BB_PER_CTX_PTR */ \
498 REG(0x1c4), /* [0x14] RCS_INDIRECT_CTX */ \
499 REG(0x1c8), /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
500 REG(0x180), /* [0x18] CCID */ \
501 REG16(0x2b4), /* [0x1a] SEMAPHORE_TOKEN */ \
502 REG(0x120), /* [0x1c] PRT_BB_STATE */ \
503 REG(0x124), /* [0x1e] PRT_BB_STATE_UDW */ \
505 NOP(1), /* [0x20] */ \
506 LRI(9, POSTED), /* [0x21] */ \
507 REG16(0x3a8), /* [0x22] CTX_TIMESTAMP */ \
508 REG16(0x3ac), /* [0x24] CTX_TIMESTAMP_UDW */ \
509 REG(0x108), /* [0x26] INDIRECT_RING_STATE */ \
510 REG16(0x284), /* [0x28] dummy reg */ \
511 REG16(0x280), /* [0x2a] CS_ACC_CTR_THOLD */ \
512 REG16(0x27c), /* [0x2c] CS_CTX_SYS_PASID */ \
513 REG16(0x278), /* [0x2e] CS_CTX_ASID */ \
514 REG16(0x274), /* [0x30] PTBP_UDW */ \
515 REG16(0x270) /* [0x32] PTBP_LDW */
520 NOP(2), /* [0x34] */
521 LRI(2, POSTED), /* [0x36] */
522 REG16(0x5a8), /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */
523 REG16(0x5ac), /* [0x39] PREEMPTION_STATUS */
525 NOP(6), /* [0x41] */
526 LRI(1, 0), /* [0x47] */
527 REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */
529 0
535 NOP(4 + 8 + 1), /* [0x34] */
536 LRI(2, POSTED), /* [0x41] */
537 REG16(0x200), /* [0x42] BCS_SWCTRL */
538 REG16(0x204), /* [0x44] BLIT_CCTL */
540 0
546 0
550 NOP(1), /* [0x00] */
551 LRI(5, POSTED), /* [0x01] */
552 REG(0x034), /* [0x02] RING_BUFFER_HEAD */
553 REG(0x030), /* [0x04] RING_BUFFER_TAIL */
554 REG(0x038), /* [0x06] RING_BUFFER_START */
555 REG(0x048), /* [0x08] RING_BUFFER_START_UDW */
556 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */
558 NOP(5), /* [0x0c] */
559 LRI(9, POSTED), /* [0x11] */
560 REG(0x168), /* [0x12] BB_ADDR_UDW */
561 REG(0x140), /* [0x14] BB_ADDR */
562 REG(0x110), /* [0x16] BB_STATE */
563 REG16(0x588), /* [0x18] BB_STACK_WRITE_PORT */
564 REG16(0x588), /* [0x20] BB_STACK_WRITE_PORT */
565 REG16(0x588), /* [0x22] BB_STACK_WRITE_PORT */
566 REG16(0x588), /* [0x24] BB_STACK_WRITE_PORT */
567 REG16(0x588), /* [0x26] BB_STACK_WRITE_PORT */
568 REG16(0x588), /* [0x28] BB_STACK_WRITE_PORT */
570 NOP(12), /* [0x00] */
572 0
629 regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr; in set_memory_based_intr()
635 regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr; in set_memory_based_intr()
637 regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr; in set_memory_based_intr()
641 regs[CTX_CS_INT_VEC_REG] = CS_INT_VEC(0).addr; in set_memory_based_intr()
651 return 0x70; in lrc_ring_mi_mode()
653 return 0x60; in lrc_ring_mi_mode()
672 return 0; in __xe_lrc_ring_offset()
828 u32 ldw, udw = 0; in xe_lrc_ctx_timestamp()
875 return 0; in xe_lrc_indirect_ring_ggtt_addr()
971 * the LRC. The value chosen is 1 since 0 is the initial value when the LRC is
998 *cmd++ = ENGINE_ID(0).addr; in setup_utilization_wa()
1000 *cmd++ = 0; in setup_utilization_wa()
1004 *cmd++ = 0; in setup_utilization_wa()
1010 *cmd++ = 0; in setup_utilization_wa()
1054 for (size_t i = 0; i < state->num_funcs; i++) { in setup_bo()
1063 if (len < 0 || in setup_bo()
1071 return 0; in setup_bo()
1117 return 0; in setup_wa_bb()
1134 return 0; in setup_indirect_ctx()
1143 return 0; in setup_indirect_ctx()
1153 while (state.written & 0xf) { in setup_indirect_ctx()
1169 return 0; in setup_indirect_ctx()
1189 lrc->flags = 0; in xe_lrc_init()
1191 lrc->ring.tail = 0; in xe_lrc_init()
1223 xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE); /* PPHWSP */ in xe_lrc_init()
1235 xe_map_memcpy_to(xe, &map, 0, init_data, lrc_size); in xe_lrc_init()
1260 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0); in xe_lrc_init()
1261 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0); in xe_lrc_init()
1267 xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0); in xe_lrc_init()
1283 lrc->ctx_timestamp = 0; in xe_lrc_init()
1284 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0); in xe_lrc_init()
1286 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP_UDW, 0); in xe_lrc_init()
1323 return 0; in xe_lrc_init()
1366 * Called when ref == 0, release resources held by the Logical Ring Context
1432 xe_map_memcpy_to(xe, &ring, 0, data, size); in __xe_lrc_write_ring()
1561 GFXPIPE_SINGLE_DW_CMD(0, 0)) in instr_dw()
1568 /* Most instructions have the # of dwords (minus 2) in 7:0 */ in instr_dw()
1620 dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "", in dump_mi_command()
1621 dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : ""); in dump_mi_command()
1838 while (remaining_dw > 0) { in xe_lrc_dump_default()
1920 int state_table_size = 0; in xe_lrc_emit_hwe_state_instructions()
1926 * setting up the default LRC, the context switch will write 0's in xe_lrc_emit_hwe_state_instructions()
1953 for (int i = 0; i < state_table_size; i++) { in xe_lrc_emit_hwe_state_instructions()
1959 xe_gt_assert(gt, num_dw != 0); in xe_lrc_emit_hwe_state_instructions()
2045 drm_printf(p, "\tHW Context Desc: 0x%08x\n", snapshot->context_desc); in xe_lrc_snapshot_print()
2046 drm_printf(p, "\tHW Ring address: 0x%08x\n", in xe_lrc_snapshot_print()
2048 drm_printf(p, "\tHW Indirect Ring State: 0x%08x\n", in xe_lrc_snapshot_print()
2053 drm_printf(p, "\tRing start: (memory) 0x%08x\n", snapshot->start); in xe_lrc_snapshot_print()
2056 drm_printf(p, "\tTimestamp: 0x%08x\n", snapshot->ctx_timestamp); in xe_lrc_snapshot_print()
2057 drm_printf(p, "\tJob Timestamp: 0x%08x\n", snapshot->ctx_job_timestamp); in xe_lrc_snapshot_print()
2062 drm_printf(p, "\t[HWSP].length: 0x%x\n", LRC_PPHWSP_SIZE); in xe_lrc_snapshot_print()
2064 for (i = 0; i < LRC_PPHWSP_SIZE; i += sizeof(u32)) { in xe_lrc_snapshot_print()
2071 drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE); in xe_lrc_snapshot_print()
2116 return 0; in get_ctx_timestamp()