Lines Matching +full:0 +full:x1c8
33 #define LRC_VALID BIT_ULL(0)
98 * [5:0]: Number of NOPs or registers to set values to in case of
103 * is used for offsets smaller than 0x200 while the latter is for values bigger
108 * [6:0]: Register offset, without considering the engine base.
119 #define POSTED BIT(0) in set_offsets()
120 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
122 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
123 (((x) >> 2) & 0x7f) in set_offsets()
136 count = *data & 0x3f; in set_offsets()
148 u32 offset = 0; in set_offsets()
157 regs[0] = base + (offset << 2); in set_offsets()
162 *regs = MI_BATCH_BUFFER_END | BIT(0); in set_offsets()
168 REG16(0x244),
169 REG(0x034),
170 REG(0x030),
171 REG(0x038),
172 REG(0x03c),
173 REG(0x168),
174 REG(0x140),
175 REG(0x110),
176 REG(0x1c0),
177 REG(0x1c4),
178 REG(0x1c8),
179 REG(0x180),
180 REG16(0x2b4),
184 REG16(0x3a8),
185 REG16(0x28c),
186 REG16(0x288),
187 REG16(0x284),
188 REG16(0x280),
189 REG16(0x27c),
190 REG16(0x278),
191 REG16(0x274),
192 REG16(0x270),
194 0
200 REG16(0x244),
201 REG(0x034),
202 REG(0x030),
203 REG(0x038),
204 REG(0x03c),
205 REG(0x168),
206 REG(0x140),
207 REG(0x110),
208 REG(0x1c0),
209 REG(0x1c4),
210 REG(0x1c8),
211 REG(0x180),
212 REG16(0x2b4),
213 REG(0x120),
214 REG(0x124),
218 REG16(0x3a8),
219 REG16(0x28c),
220 REG16(0x288),
221 REG16(0x284),
222 REG16(0x280),
223 REG16(0x27c),
224 REG16(0x278),
225 REG16(0x274),
226 REG16(0x270),
228 0
234 REG16(0x244),
235 REG(0x034),
236 REG(0x030),
237 REG(0x038),
238 REG(0x03c),
239 REG(0x168),
240 REG(0x140),
241 REG(0x110),
242 REG(0x1c0),
243 REG(0x1c4),
244 REG(0x1c8),
245 REG(0x180),
246 REG16(0x2b4),
250 REG16(0x3a8),
251 REG16(0x28c),
252 REG16(0x288),
253 REG16(0x284),
254 REG16(0x280),
255 REG16(0x27c),
256 REG16(0x278),
257 REG16(0x274),
258 REG16(0x270),
261 REG(0x1b0),
262 REG16(0x5a8),
263 REG16(0x5ac),
266 LRI(1, 0),
267 REG(0x0c8),
271 REG16(0x588),
272 REG16(0x588),
273 REG16(0x588),
274 REG16(0x588),
275 REG16(0x588),
276 REG16(0x588),
277 REG(0x028),
278 REG(0x09c),
279 REG(0x0c0),
280 REG(0x178),
281 REG(0x17c),
282 REG16(0x358),
283 REG(0x170),
284 REG(0x150),
285 REG(0x154),
286 REG(0x158),
287 REG16(0x41c),
288 REG16(0x600),
289 REG16(0x604),
290 REG16(0x608),
291 REG16(0x60c),
292 REG16(0x610),
293 REG16(0x614),
294 REG16(0x618),
295 REG16(0x61c),
296 REG16(0x620),
297 REG16(0x624),
298 REG16(0x628),
299 REG16(0x62c),
300 REG16(0x630),
301 REG16(0x634),
302 REG16(0x638),
303 REG16(0x63c),
304 REG16(0x640),
305 REG16(0x644),
306 REG16(0x648),
307 REG16(0x64c),
308 REG16(0x650),
309 REG16(0x654),
310 REG16(0x658),
311 REG16(0x65c),
312 REG16(0x660),
313 REG16(0x664),
314 REG16(0x668),
315 REG16(0x66c),
316 REG16(0x670),
317 REG16(0x674),
318 REG16(0x678),
319 REG16(0x67c),
320 REG(0x068),
321 REG(0x084),
324 0
330 REG16(0x244),
331 REG(0x034),
332 REG(0x030),
333 REG(0x038),
334 REG(0x03c),
335 REG(0x168),
336 REG(0x140),
337 REG(0x110),
338 REG(0x1c0),
339 REG(0x1c4),
340 REG(0x1c8),
341 REG(0x180),
342 REG16(0x2b4),
346 REG16(0x3a8),
347 REG16(0x28c),
348 REG16(0x288),
349 REG16(0x284),
350 REG16(0x280),
351 REG16(0x27c),
352 REG16(0x278),
353 REG16(0x274),
354 REG16(0x270),
357 REG(0x1b0),
358 REG16(0x5a8),
359 REG16(0x5ac),
362 LRI(1, 0),
363 REG(0x0c8),
365 0
371 REG16(0x244),
372 REG(0x034),
373 REG(0x030),
374 REG(0x038),
375 REG(0x03c),
376 REG(0x168),
377 REG(0x140),
378 REG(0x110),
379 REG(0x1c0),
380 REG(0x1c4),
381 REG(0x1c8),
382 REG(0x180),
383 REG16(0x2b4),
384 REG(0x120),
385 REG(0x124),
389 REG16(0x3a8),
390 REG16(0x28c),
391 REG16(0x288),
392 REG16(0x284),
393 REG16(0x280),
394 REG16(0x27c),
395 REG16(0x278),
396 REG16(0x274),
397 REG16(0x270),
400 REG(0x1b0),
401 REG16(0x5a8),
402 REG16(0x5ac),
405 LRI(1, 0),
406 REG(0x0c8),
408 0
414 REG16(0x244),
415 REG(0x034),
416 REG(0x030),
417 REG(0x038),
418 REG(0x03c),
419 REG(0x168),
420 REG(0x140),
421 REG(0x110),
422 REG(0x1c0),
423 REG(0x1c4),
424 REG(0x1c8),
425 REG(0x180),
426 REG16(0x2b4),
427 REG(0x120),
428 REG(0x124),
432 REG16(0x3a8),
433 REG16(0x28c),
434 REG16(0x288),
435 REG16(0x284),
436 REG16(0x280),
437 REG16(0x27c),
438 REG16(0x278),
439 REG16(0x274),
440 REG16(0x270),
444 REG16(0x5a8),
445 REG16(0x5ac),
448 LRI(1, 0),
449 REG(0x0c8),
451 0
455 NOP(1), /* [0x00] */ \
456 LRI(15, POSTED), /* [0x01] */ \
457 REG16(0x244), /* [0x02] CTXT_SR_CTL */ \
458 REG(0x034), /* [0x04] RING_BUFFER_HEAD */ \
459 REG(0x030), /* [0x06] RING_BUFFER_TAIL */ \
460 REG(0x038), /* [0x08] RING_BUFFER_START */ \
461 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ \
462 REG(0x168), /* [0x0c] BB_ADDR_UDW */ \
463 REG(0x140), /* [0x0e] BB_ADDR */ \
464 REG(0x110), /* [0x10] BB_STATE */ \
465 REG(0x1c0), /* [0x12] BB_PER_CTX_PTR */ \
466 REG(0x1c4), /* [0x14] RCS_INDIRECT_CTX */ \
467 REG(0x1c8), /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
468 REG(0x180), /* [0x18] CCID */ \
469 REG16(0x2b4), /* [0x1a] SEMAPHORE_TOKEN */ \
470 REG(0x120), /* [0x1c] PRT_BB_STATE */ \
471 REG(0x124), /* [0x1e] PRT_BB_STATE_UDW */ \
473 NOP(1), /* [0x20] */ \
474 LRI(9, POSTED), /* [0x21] */ \
475 REG16(0x3a8), /* [0x22] CTX_TIMESTAMP */ \
476 REG16(0x3ac), /* [0x24] CTX_TIMESTAMP_UDW */ \
477 REG(0x108), /* [0x26] INDIRECT_RING_STATE */ \
478 REG16(0x284), /* [0x28] dummy reg */ \
479 REG16(0x280), /* [0x2a] CS_ACC_CTR_THOLD */ \
480 REG16(0x27c), /* [0x2c] CS_CTX_SYS_PASID */ \
481 REG16(0x278), /* [0x2e] CS_CTX_ASID */ \
482 REG16(0x274), /* [0x30] PTBP_UDW */ \
483 REG16(0x270) /* [0x32] PTBP_LDW */
488 NOP(2), /* [0x34] */
489 LRI(2, POSTED), /* [0x36] */
490 REG16(0x5a8), /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */
491 REG16(0x5ac), /* [0x39] PREEMPTION_STATUS */
493 NOP(6), /* [0x41] */
494 LRI(1, 0), /* [0x47] */
495 REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */
497 0
503 NOP(4 + 8 + 1), /* [0x34] */
504 LRI(2, POSTED), /* [0x41] */
505 REG16(0x200), /* [0x42] BCS_SWCTRL */
506 REG16(0x204), /* [0x44] BLIT_CCTL */
508 0
514 0
518 NOP(1), /* [0x00] */
519 LRI(5, POSTED), /* [0x01] */
520 REG(0x034), /* [0x02] RING_BUFFER_HEAD */
521 REG(0x030), /* [0x04] RING_BUFFER_TAIL */
522 REG(0x038), /* [0x06] RING_BUFFER_START */
523 REG(0x048), /* [0x08] RING_BUFFER_START_UDW */
524 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */
526 NOP(5), /* [0x0c] */
527 LRI(9, POSTED), /* [0x11] */
528 REG(0x168), /* [0x12] BB_ADDR_UDW */
529 REG(0x140), /* [0x14] BB_ADDR */
530 REG(0x110), /* [0x16] BB_STATE */
531 REG16(0x588), /* [0x18] BB_STACK_WRITE_PORT */
532 REG16(0x588), /* [0x20] BB_STACK_WRITE_PORT */
533 REG16(0x588), /* [0x22] BB_STACK_WRITE_PORT */
534 REG16(0x588), /* [0x24] BB_STACK_WRITE_PORT */
535 REG16(0x588), /* [0x26] BB_STACK_WRITE_PORT */
536 REG16(0x588), /* [0x28] BB_STACK_WRITE_PORT */
538 NOP(12), /* [0x00] */
540 0
599 regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr; in set_memory_based_intr()
605 regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr; in set_memory_based_intr()
607 regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr; in set_memory_based_intr()
611 regs[CTX_CS_INT_VEC_REG] = CS_INT_VEC(0).addr; in set_memory_based_intr()
621 return 0x70; in lrc_ring_mi_mode()
623 return 0x60; in lrc_ring_mi_mode()
642 return 0; in __xe_lrc_ring_offset()
783 u32 ldw, udw = 0; in xe_lrc_ctx_timestamp()
830 return 0; in xe_lrc_indirect_ring_ggtt_addr()
928 * the LRC. The value chosen is 1 since 0 is the initial value when the LRC is
958 *cmd++ = ENGINE_ID(0).addr; in xe_lrc_setup_utilization()
960 *cmd++ = 0; in xe_lrc_setup_utilization()
964 *cmd++ = 0; in xe_lrc_setup_utilization()
970 *cmd++ = 0; in xe_lrc_setup_utilization()
977 xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bb_per_ctx_bo->vmap, 0, in xe_lrc_setup_utilization()
985 return 0; in xe_lrc_setup_utilization()
988 #define PVC_CTX_ASID (0x2e + 1)
989 #define PVC_CTX_ACC_CTR_THOLD (0x2a + 1)
1007 lrc->flags = 0; in xe_lrc_init()
1037 lrc->ring.tail = 0; in xe_lrc_init()
1056 xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE); /* PPHWSP */ in xe_lrc_init()
1061 xe_map_memcpy_to(xe, &map, 0, init_data, in xe_lrc_init()
1087 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_START_UDW, 0); in xe_lrc_init()
1088 xe_lrc_write_indirect_ctx_reg(lrc, INDIRECT_CTX_RING_HEAD, 0); in xe_lrc_init()
1094 xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0); in xe_lrc_init()
1110 lrc->ctx_timestamp = 0; in xe_lrc_init()
1111 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP, 0); in xe_lrc_init()
1113 xe_lrc_write_ctx_reg(lrc, CTX_TIMESTAMP_UDW, 0); in xe_lrc_init()
1146 return 0; in xe_lrc_init()
1189 * Called when ref == 0, release resources held by the Logical Ring Context
1255 xe_map_memcpy_to(xe, &ring, 0, data, size); in __xe_lrc_write_ring()
1384 GFXPIPE_SINGLE_DW_CMD(0, 0)) in instr_dw()
1391 /* Most instructions have the # of dwords (minus 2) in 7:0 */ in instr_dw()
1443 dw[0] & MI_LRI_LRM_CS_MMIO ? "CS_MMIO " : "", in dump_mi_command()
1444 dw[0] & MI_LRM_USE_GGTT ? "USE_GGTT " : ""); in dump_mi_command()
1661 while (remaining_dw > 0) { in xe_lrc_dump_default()
1743 int state_table_size = 0; in xe_lrc_emit_hwe_state_instructions()
1749 * setting up the default LRC, the context switch will write 0's in xe_lrc_emit_hwe_state_instructions()
1776 for (int i = 0; i < state_table_size; i++) { in xe_lrc_emit_hwe_state_instructions()
1782 xe_gt_assert(gt, num_dw != 0); in xe_lrc_emit_hwe_state_instructions()
1866 drm_printf(p, "\tHW Context Desc: 0x%08x\n", snapshot->context_desc); in xe_lrc_snapshot_print()
1867 drm_printf(p, "\tHW Ring address: 0x%08x\n", in xe_lrc_snapshot_print()
1869 drm_printf(p, "\tHW Indirect Ring State: 0x%08x\n", in xe_lrc_snapshot_print()
1874 drm_printf(p, "\tRing start: (memory) 0x%08x\n", snapshot->start); in xe_lrc_snapshot_print()
1877 drm_printf(p, "\tTimestamp: 0x%08x\n", snapshot->ctx_timestamp); in xe_lrc_snapshot_print()
1878 drm_printf(p, "\tJob Timestamp: 0x%08x\n", snapshot->ctx_job_timestamp); in xe_lrc_snapshot_print()
1883 drm_printf(p, "\t[HWSP].length: 0x%x\n", LRC_PPHWSP_SIZE); in xe_lrc_snapshot_print()
1885 for (i = 0; i < LRC_PPHWSP_SIZE; i += sizeof(u32)) { in xe_lrc_snapshot_print()
1892 drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE); in xe_lrc_snapshot_print()
1937 return 0; in get_ctx_timestamp()