Lines Matching +full:0 +full:xe
68 #define PWR_UNIT 0x3
69 #define ENERGY_UNIT 0xe
70 #define TIME_UNIT 0xa
115 * struct xe_hwmon - xe hwmon data structure
118 /** @hwmon_dev: hwmon device for xe */
120 /** @xe: Xe device */
121 struct xe_device *xe; member
146 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); in xe_hwmon_pcode_read_power_limit()
147 u32 val0 = 0, val1 = 0; in xe_hwmon_pcode_read_power_limit()
148 int ret = 0; in xe_hwmon_pcode_read_power_limit()
159 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", in xe_hwmon_pcode_read_power_limit()
161 *uval = 0; in xe_hwmon_pcode_read_power_limit()
167 *uval = (val0 & PWR_LIM_EN) ? val0 : 0; in xe_hwmon_pcode_read_power_limit()
169 *uval = (val1 & PWR_LIM_EN) ? val1 : 0; in xe_hwmon_pcode_read_power_limit()
171 *uval = (val0 & PWR_LIM_EN) ? 1 : (val1 & PWR_LIM_EN) ? 1 : 0; in xe_hwmon_pcode_read_power_limit()
173 *uval = 0; in xe_hwmon_pcode_read_power_limit()
181 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); in xe_hwmon_pcode_rmw_power_limit()
183 int ret = 0; in xe_hwmon_pcode_rmw_power_limit()
194 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", in xe_hwmon_pcode_rmw_power_limit()
207 WRITE_PACKAGE_POWER_LIMIT, 0), in xe_hwmon_pcode_rmw_power_limit()
210 drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", in xe_hwmon_pcode_rmw_power_limit()
218 struct xe_device *xe = hwmon->xe; in xe_hwmon_get_reg() local
222 if (xe->info.platform == XE_BATTLEMAGE) { in xe_hwmon_get_reg()
227 } else if (xe->info.platform == XE_DG2) { in xe_hwmon_get_reg()
235 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) in xe_hwmon_get_reg()
237 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) in xe_hwmon_get_reg()
241 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) in xe_hwmon_get_reg()
243 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) in xe_hwmon_get_reg()
247 if (xe->info.platform == XE_PVC) in xe_hwmon_get_reg()
249 else if (xe->info.platform == XE_DG2) in xe_hwmon_get_reg()
253 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) in xe_hwmon_get_reg()
257 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { in xe_hwmon_get_reg()
259 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { in xe_hwmon_get_reg()
272 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); in xe_hwmon_get_reg()
276 return XE_REG(0); in xe_hwmon_get_reg()
279 #define PL_DISABLE 0
289 u64 reg_val = 0, min, max; in xe_hwmon_power_max_read()
290 struct xe_device *xe = hwmon->xe; in xe_hwmon_power_max_read() local
292 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in xe_hwmon_power_max_read()
296 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_max_read()
307 drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%016llx\n", in xe_hwmon_power_max_read()
316 if (!hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_max_read()
331 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_power_max_write()
332 int ret = 0; in xe_hwmon_power_max_write()
342 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_max_write()
343 drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n", in xe_hwmon_power_max_write()
345 xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0); in xe_hwmon_power_max_write()
348 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0); in xe_hwmon_power_max_write()
353 drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n"); in xe_hwmon_power_max_write()
366 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_max_write()
372 drm_dbg(&hwmon->xe->drm, in xe_hwmon_power_max_write()
373 "Clamping power limit to GPU firmware default 0x%x\n", in xe_hwmon_power_max_write()
380 if (hwmon->xe->info.has_mbx_power_limits) in xe_hwmon_power_max_write()
392 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_power_rated_max_read()
395 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_rated_max_read()
436 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_energy_get()
439 int ret = 0; in xe_hwmon_energy_get()
443 *energy = 0; in xe_hwmon_energy_get()
447 if (hwmon->xe->info.platform == XE_BATTLEMAGE) { in xe_hwmon_energy_get()
450 ret = xe_pmt_telem_read(to_pci_dev(hwmon->xe->drm.dev), in xe_hwmon_energy_get()
454 drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret); in xe_hwmon_energy_get()
455 *energy = 0; in xe_hwmon_energy_get()
480 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_power_max_interval_show()
486 int ret = 0; in xe_hwmon_power_max_interval_show()
488 xe_pm_runtime_get(hwmon->xe); in xe_hwmon_power_max_interval_show()
492 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_max_interval_show()
495 drm_err(&hwmon->xe->drm, in xe_hwmon_power_max_interval_show()
496 "power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n", in xe_hwmon_power_max_interval_show()
498 r = 0; in xe_hwmon_power_max_interval_show()
506 xe_pm_runtime_put(hwmon->xe); in xe_hwmon_power_max_interval_show()
534 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_power_max_interval_store()
542 ret = kstrtoul(buf, 0, &val); in xe_hwmon_power_max_interval_store()
547 * Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12. in xe_hwmon_power_max_interval_store()
548 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. in xe_hwmon_power_max_interval_store()
555 #define PKG_MAX_WIN_DEFAULT 0x12ull in xe_hwmon_power_max_interval_store()
579 y = 0; in xe_hwmon_power_max_interval_store()
580 x = 0; in xe_hwmon_power_max_interval_store()
589 xe_pm_runtime_get(hwmon->xe); in xe_hwmon_power_max_interval_store()
593 if (hwmon->xe->info.has_mbx_power_limits) in xe_hwmon_power_max_interval_store()
601 xe_pm_runtime_put(hwmon->xe); in xe_hwmon_power_max_interval_store()
636 int ret = 0; in xe_hwmon_attributes_visible()
639 u32 uval = 0; in xe_hwmon_attributes_visible()
641 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_attributes_visible()
643 xe_pm_runtime_get(hwmon->xe); in xe_hwmon_attributes_visible()
645 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_attributes_visible()
652 ret = (uval & PWR_LIM_EN) ? attr->mode : 0; in xe_hwmon_attributes_visible()
654 xe_pm_runtime_put(hwmon->xe); in xe_hwmon_attributes_visible()
685 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); in xe_hwmon_pcode_read_i1()
688 if (hwmon->xe->info.platform == XE_DG2) in xe_hwmon_pcode_read_i1()
692 POWER_SETUP_SUBCOMMAND_READ_I1, 0), in xe_hwmon_pcode_read_i1()
698 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); in xe_hwmon_pcode_write_i1()
701 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), in xe_hwmon_pcode_write_i1()
707 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); in xe_hwmon_pcode_read_fan_control()
710 if (hwmon->xe->info.platform == XE_DG2 && subcmd == FSC_READ_NUM_FANS) { in xe_hwmon_pcode_read_fan_control()
712 return 0; in xe_hwmon_pcode_read_fan_control()
715 return xe_pcode_read(root_tile, PCODE_MBOX(FAN_SPEED_CONTROL, subcmd, 0), uval, NULL); in xe_hwmon_pcode_read_fan_control()
754 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_get_voltage()
768 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0; in xe_hwmon_temp_is_visible()
770 return 0; in xe_hwmon_temp_is_visible()
777 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_temp_read()
786 return 0; in xe_hwmon_temp_read()
795 u32 uval = 0; in xe_hwmon_power_is_visible()
797 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_power_is_visible()
802 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_is_visible()
810 drm_info(&hwmon->xe->drm, "%s is supported on channel %d\n", in xe_hwmon_power_is_visible()
814 drm_dbg(&hwmon->xe->drm, "%s is unsupported on channel %d\n", in xe_hwmon_power_is_visible()
816 return 0; in xe_hwmon_power_is_visible()
818 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_is_visible()
819 return 0; in xe_hwmon_power_is_visible()
824 return uval ? 0444 : 0; in xe_hwmon_power_is_visible()
829 return (uval & POWER_SETUP_I1_WATTS) ? 0644 : 0; in xe_hwmon_power_is_visible()
833 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_power_is_visible()
848 return (uval & POWER_SETUP_I1_WATTS) ? 0444 : 0; in xe_hwmon_power_is_visible()
850 return (uval) ? 0444 : 0; in xe_hwmon_power_is_visible()
852 return 0; in xe_hwmon_power_is_visible()
854 return 0; in xe_hwmon_power_is_visible()
864 return 0; in xe_hwmon_power_read()
867 return 0; in xe_hwmon_power_read()
896 return 0; in xe_hwmon_curr_is_visible()
901 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; in xe_hwmon_curr_is_visible()
904 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; in xe_hwmon_curr_is_visible()
907 return 0; in xe_hwmon_curr_is_visible()
909 return 0; in xe_hwmon_curr_is_visible()
941 channel)) ? 0444 : 0; in xe_hwmon_in_is_visible()
943 return 0; in xe_hwmon_in_is_visible()
953 return 0; in xe_hwmon_in_read()
962 long energy = 0; in xe_hwmon_energy_is_visible()
967 if (hwmon->xe->info.platform == XE_BATTLEMAGE) { in xe_hwmon_energy_is_visible()
969 return energy ? 0444 : 0; in xe_hwmon_energy_is_visible()
972 channel)) ? 0444 : 0; in xe_hwmon_energy_is_visible()
975 return 0; in xe_hwmon_energy_is_visible()
985 return 0; in xe_hwmon_energy_read()
996 if (!hwmon->xe->info.has_fan_control) in xe_hwmon_fan_is_visible()
997 return 0; in xe_hwmon_fan_is_visible()
1002 return 0; in xe_hwmon_fan_is_visible()
1004 return channel < uval ? 0444 : 0; in xe_hwmon_fan_is_visible()
1006 return 0; in xe_hwmon_fan_is_visible()
1013 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_fan_input_read()
1017 int ret = 0; in xe_hwmon_fan_input_read()
1067 xe_pm_runtime_get(hwmon->xe); in xe_hwmon_is_visible()
1089 ret = 0; in xe_hwmon_is_visible()
1093 xe_pm_runtime_put(hwmon->xe); in xe_hwmon_is_visible()
1105 xe_pm_runtime_get(hwmon->xe); in xe_hwmon_read()
1131 xe_pm_runtime_put(hwmon->xe); in xe_hwmon_read()
1143 xe_pm_runtime_get(hwmon->xe); in xe_hwmon_write()
1157 xe_pm_runtime_put(hwmon->xe); in xe_hwmon_write()
1172 return 0; in xe_hwmon_read_label()
1181 return 0; in xe_hwmon_read_label()
1202 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); in xe_hwmon_get_preregistration_info()
1204 u64 val_sku_unit = 0; in xe_hwmon_get_preregistration_info()
1208 if (hwmon->xe->info.has_mbx_power_limits) { in xe_hwmon_get_preregistration_info()
1218 drm_warn(&hwmon->xe->drm, in xe_hwmon_get_preregistration_info()
1221 drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n"); in xe_hwmon_get_preregistration_info()
1241 drm_info(&hwmon->xe->drm, "Using register for power limits\n"); in xe_hwmon_get_preregistration_info()
1246 pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0); in xe_hwmon_get_preregistration_info()
1258 for (channel = 0; channel < CHANNEL_MAX; channel++) in xe_hwmon_get_preregistration_info()
1263 for (channel = 0; channel < FAN_MAX; channel++) in xe_hwmon_get_preregistration_info()
1275 int xe_hwmon_register(struct xe_device *xe) in xe_hwmon_register() argument
1277 struct device *dev = xe->drm.dev; in xe_hwmon_register()
1282 if (!IS_DGFX(xe)) in xe_hwmon_register()
1283 return 0; in xe_hwmon_register()
1286 if (IS_SRIOV_VF(xe)) in xe_hwmon_register()
1287 return 0; in xe_hwmon_register()
1299 hwmon->xe = xe; in xe_hwmon_register()
1300 xe->hwmon = hwmon; in xe_hwmon_register()
1304 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); in xe_hwmon_register()
1307 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, in xe_hwmon_register()
1311 drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); in xe_hwmon_register()
1312 xe->hwmon = NULL; in xe_hwmon_register()
1316 return 0; in xe_hwmon_register()