Lines Matching +full:per +full:- +full:slice
1 // SPDX-License-Identifier: MIT
24 * independent values of a register per hardware unit (e.g., per-subslice,
25 * per-L3bank, etc.). The specific types of replication that exist vary
26 * per-platform.
42 * ``init_steering_*()`` functions is to apply the platform-specific rules for
44 * non-terminated instance.
79 { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
91 * provide us with a non-terminated value. We'll stick them all in the same
95 { 0x004000, 0x004AFF }, /* HALF-BSLICE */
98 { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
100 { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
101 { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
103 { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
104 { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
105 { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
106 { 0x024180, 0x0241FF }, /* HALF-BSLICE */
139 { 0x008140, 0x00815F }, /* GSLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
141 { 0x0094D0, 0x00955F }, /* GSLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
145 { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved ) */
153 { 0x008140, 0x00817F }, /* COMPUTE (0x8140-0x814F & 0x8160-0x817F), DSS (0x8150-0x815F) */
154 { 0x0094D0, 0x00955F }, /* COMPUTE (0x94D0-0x951F), DSS (0x9520-0x955F) */
157 { 0x00DE80, 0x00E7FF }, /* DSS (0xDF00-0xE1FF reserved ) */
161 /* DSS steering is used for SLICE ranges as well */
163 { 0x005200, 0x0052FF }, /* SLICE */
164 { 0x005500, 0x007FFF }, /* SLICE */
165 { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
166 { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
168 { 0x00D800, 0x00D87F }, /* SLICE */
169 { 0x00DC00, 0x00DCFF }, /* SLICE */
170 { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
191 { 0x005200, 0x0052FF }, /* SLICE */
192 { 0x005500, 0x007FFF }, /* SLICE */
193 { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
194 { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
196 { 0x00D800, 0x00D87F }, /* SLICE */
197 { 0x00DC00, 0x00DCFF }, /* SLICE */
198 { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
199 { 0x00E980, 0x00E9FF }, /* SLICE */
200 { 0x013000, 0x0133FF }, /* DSS (0x13000-0x131FF), SLICE (0x13200-0x133FF) */
253 struct xe_mmio *mmio = >->mmio; in init_steering_l3bank()
265 gt->steering[L3BANK].group_target = __ffs(mslice_mask); in init_steering_l3bank()
266 gt->steering[L3BANK].instance_target = in init_steering_l3bank()
268 } else if (gt_to_xe(gt)->info.platform == XE_DG2) { in init_steering_l3bank()
278 gt->steering[L3BANK].group_target = (bank >> 2) & 0x7; in init_steering_l3bank()
279 gt->steering[L3BANK].instance_target = bank & 0x3; in init_steering_l3bank()
284 gt->steering[L3BANK].group_target = 0; /* unused */ in init_steering_l3bank()
285 gt->steering[L3BANK].instance_target = __ffs(fuse); in init_steering_l3bank()
292 xe_mmio_read32(>->mmio, MIRROR_FUSE3)); in init_steering_mslice()
298 * so we can just use that to find a non-terminated mslice and ignore in init_steering_mslice()
301 gt->steering[MSLICE].group_target = __ffs(mask); in init_steering_mslice()
302 gt->steering[MSLICE].instance_target = 0; /* unused */ in init_steering_mslice()
306 * it up here. Either LNCF within a non-terminated mslice will work, in init_steering_mslice()
309 gt->steering[LNCF].group_target = __ffs(mask) << 1; in init_steering_mslice()
310 gt->steering[LNCF].instance_target = 0; /* unused */ in init_steering_mslice()
315 struct xe_guc *guc = >->uc.guc; in dss_per_group()
322 * slice/DSS counts, just the physical layout by which we should in dss_per_group()
349 !gt_to_xe(gt)->info.force_execlist) in dss_per_group()
350 …xe_gt_err(gt, "Slice/Subslice counts missing from hwconfig table; using typical fallback values\n"… in dss_per_group()
352 if (gt_to_xe(gt)->info.platform == XE_PVC) in dss_per_group()
361 * xe_gt_mcr_get_dss_steering - Get the group/instance steering for a DSS
371 *group = dss / gt->steering_dss_per_grp; in xe_gt_mcr_get_dss_steering()
372 *instance = dss % gt->steering_dss_per_grp; in xe_gt_mcr_get_dss_steering()
376 * xe_gt_mcr_steering_info_to_dss_id - Get DSS ID from group/instance steering
390 gt->steering_dss_per_grp = dss_per_group(gt); in init_steering_dss()
393 min(xe_dss_mask_group_ffs(gt->fuse_topo.g_dss_mask, 0, 0), in init_steering_dss()
394 xe_dss_mask_group_ffs(gt->fuse_topo.c_dss_mask, 0, 0)), in init_steering_dss()
395 >->steering[DSS].group_target, in init_steering_dss()
396 >->steering[DSS].instance_target); in init_steering_dss()
402 * First instance is only terminated if the entire first media slice in init_steering_oaddrm()
405 if (gt->info.engine_mask & (XE_HW_ENGINE_VCS0 | XE_HW_ENGINE_VECS0)) in init_steering_oaddrm()
406 gt->steering[OADDRM].group_target = 0; in init_steering_oaddrm()
408 gt->steering[OADDRM].group_target = 1; in init_steering_oaddrm()
410 gt->steering[OADDRM].instance_target = 0; /* unused */ in init_steering_oaddrm()
416 xe_mmio_read32(>->mmio, MIRROR_FUSE3)); in init_steering_sqidi_psmi()
419 gt->steering[SQIDI_PSMI].group_target = select >> 1; in init_steering_sqidi_psmi()
420 gt->steering[SQIDI_PSMI].instance_target = select & 0x1; in init_steering_sqidi_psmi()
438 * xe_gt_mcr_init_early - Early initialization of the MCR support
453 spin_lock_init(>->mcr_lock); in xe_gt_mcr_init_early()
458 if (gt->info.type == XE_GT_TYPE_MEDIA) { in xe_gt_mcr_init_early()
459 drm_WARN_ON(&xe->drm, MEDIA_VER(xe) < 13); in xe_gt_mcr_init_early()
462 gt->steering[OADDRM].ranges = xe2lpm_gpmxmt_steering_table; in xe_gt_mcr_init_early()
463 gt->steering[INSTANCE0].ranges = xe3lpm_instance0_steering_table; in xe_gt_mcr_init_early()
465 gt->steering[OADDRM].ranges = xe2lpm_gpmxmt_steering_table; in xe_gt_mcr_init_early()
466 gt->steering[INSTANCE0].ranges = xe2lpm_instance0_steering_table; in xe_gt_mcr_init_early()
468 gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table; in xe_gt_mcr_init_early()
472 gt->steering[DSS].ranges = xe2lpg_dss_steering_table; in xe_gt_mcr_init_early()
473 gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table; in xe_gt_mcr_init_early()
474 gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table; in xe_gt_mcr_init_early()
476 gt->steering[INSTANCE0].ranges = xelpg_instance0_steering_table; in xe_gt_mcr_init_early()
477 gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table; in xe_gt_mcr_init_early()
478 gt->steering[DSS].ranges = xelpg_dss_steering_table; in xe_gt_mcr_init_early()
479 } else if (xe->info.platform == XE_PVC) { in xe_gt_mcr_init_early()
480 gt->steering[INSTANCE0].ranges = xehpc_instance0_steering_table; in xe_gt_mcr_init_early()
481 gt->steering[DSS].ranges = xehpc_dss_steering_table; in xe_gt_mcr_init_early()
482 } else if (xe->info.platform == XE_DG2) { in xe_gt_mcr_init_early()
483 gt->steering[L3BANK].ranges = xehp_l3bank_steering_table; in xe_gt_mcr_init_early()
484 gt->steering[MSLICE].ranges = xehp_mslice_steering_table; in xe_gt_mcr_init_early()
485 gt->steering[LNCF].ranges = xehp_lncf_steering_table; in xe_gt_mcr_init_early()
486 gt->steering[DSS].ranges = xehp_dss_steering_table; in xe_gt_mcr_init_early()
487 gt->steering[IMPLICIT_STEERING].ranges = dg2_implicit_steering_table; in xe_gt_mcr_init_early()
489 gt->steering[L3BANK].ranges = xelp_l3bank_steering_table; in xe_gt_mcr_init_early()
490 gt->steering[DSS].ranges = xelp_dss_steering_table; in xe_gt_mcr_init_early()
495 gt->steering[INSTANCE0].initialized = true; in xe_gt_mcr_init_early()
499 * xe_gt_mcr_init - Normal initialization of the MCR support
509 /* Select non-terminated steering target for each type */ in xe_gt_mcr_init()
511 gt->steering[i].initialized = true; in xe_gt_mcr_init()
512 if (gt->steering[i].ranges && xe_steering_types[i].init) in xe_gt_mcr_init()
518 * xe_gt_mcr_set_implicit_defaults - Initialize steer control registers
522 * changed on each access - it's sufficient to set them once on initialization.
532 if (xe->info.platform == XE_DG2) { in xe_gt_mcr_set_implicit_defaults()
536 xe_mmio_write32(>->mmio, MCFG_MCR_SELECTOR, steer_val); in xe_gt_mcr_set_implicit_defaults()
537 xe_mmio_write32(>->mmio, SF_MCR_SELECTOR, steer_val); in xe_gt_mcr_set_implicit_defaults()
548 * xe_gt_mcr_get_nonterminated_steering - find group/instance values that
549 * will steer a register to a non-terminated instance
571 if (!gt->steering[type].ranges) in xe_gt_mcr_get_nonterminated_steering()
574 for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) { in xe_gt_mcr_get_nonterminated_steering()
575 if (xe_mmio_in_range(>->mmio, >->steering[type].ranges[i], reg)) { in xe_gt_mcr_get_nonterminated_steering()
576 drm_WARN(>_to_xe(gt)->drm, !gt->steering[type].initialized, in xe_gt_mcr_get_nonterminated_steering()
580 *group = gt->steering[type].group_target; in xe_gt_mcr_get_nonterminated_steering()
581 *instance = gt->steering[type].instance_target; in xe_gt_mcr_get_nonterminated_steering()
587 implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges; in xe_gt_mcr_get_nonterminated_steering()
590 if (xe_mmio_in_range(>->mmio, &implicit_ranges[i], reg)) in xe_gt_mcr_get_nonterminated_steering()
597 drm_WARN(>_to_xe(gt)->drm, true, in xe_gt_mcr_get_nonterminated_steering()
611 static void mcr_lock(struct xe_gt *gt) __acquires(>->mcr_lock) in mcr_lock()
616 spin_lock(>->mcr_lock); in mcr_lock()
625 ret = xe_mmio_wait32(>->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL, in mcr_lock()
628 drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT); in mcr_lock()
631 static void mcr_unlock(struct xe_gt *gt) __releases(>->mcr_lock) in mcr_unlock()
633 /* Release hardware semaphore - this is done by writing 1 to the register */ in mcr_unlock()
635 xe_mmio_write32(>->mmio, STEER_SEMAPHORE, 0x1); in mcr_unlock()
637 spin_unlock(>->mcr_lock); in mcr_unlock()
649 struct xe_mmio *mmio = >->mmio; in rw_with_mcr_steering()
653 lockdep_assert_held(>->mcr_lock); in rw_with_mcr_steering()
692 * don't matter since they'll be re-programmed on the next MCR in rw_with_mcr_steering()
702 * xe_gt_mcr_unicast_read_any - reads a non-terminated instance of an MCR register
706 * Reads a GT MCR register. The read will be steered to a non-terminated
711 * Returns the value from a non-terminated instance of @reg.
731 val = xe_mmio_read32(>->mmio, reg); in xe_gt_mcr_unicast_read_any()
738 * xe_gt_mcr_unicast_read - read a specific instance of an MCR register
763 * xe_gt_mcr_unicast_write - write a specific instance of an MCR register
784 * xe_gt_mcr_multicast_write - write a value to all instances of an MCR register
804 xe_mmio_write32(>->mmio, reg, value); in xe_gt_mcr_multicast_write()
811 if (gt->steering[i].ranges) { in xe_gt_mcr_steering_dump()
814 gt->steering[i].group_target, in xe_gt_mcr_steering_dump()
815 gt->steering[i].instance_target); in xe_gt_mcr_steering_dump()
816 for (int j = 0; gt->steering[i].ranges[j].end; j++) in xe_gt_mcr_steering_dump()
817 drm_printf(p, "\t0x%06x - 0x%06x\n", in xe_gt_mcr_steering_dump()
818 gt->steering[i].ranges[j].start, in xe_gt_mcr_steering_dump()
819 gt->steering[i].ranges[j].end); in xe_gt_mcr_steering_dump()