216 	for (i = 0; i < 64; i += 4) {  in vc4_hvs_dump_state()
217 		DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",  in vc4_hvs_dump_state()
219 			 readl((u32 __iomem *)hvs->dlist + i + 0),  in vc4_hvs_dump_state()
237 	return 0;  in vc4_hvs_debugfs_underrun()
252 	for (i = 0; i < SCALER_CHANNELS_COUNT; i++) {  in vc4_hvs_debugfs_dlist()
262 		next_entry_start = 0;  in vc4_hvs_debugfs_dlist()
266 			drm_printf(&p, "dlist: %02d: 0x%08x\n", j,  in vc4_hvs_debugfs_dlist()
279 	return 0;  in vc4_hvs_debugfs_dlist()
293 	for (i = 0; i < SCALER_CHANNELS_COUNT; i++) {  in vc6_hvs_debugfs_dlist()
309 		next_entry_start = 0;  in vc6_hvs_debugfs_dlist()
315 			drm_printf(&p, "dlist: %02d: 0x%08x\n", j,  in vc6_hvs_debugfs_dlist()
328 	return 0;  in vc6_hvs_debugfs_dlist()
349 	return 0;  in vc6_hvs_debugfs_upm_allocs()
355 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
357 	((((c0) & 0x1ff) << 0) |				\
358 	 (((c1) & 0x1ff) << 9) |				\
359 	 (((c2) & 0x1ff) << 18))
361 /* The whole filter kernel is arranged as the coefficients 0-16 going
374 	 VC4_PPF_FILTER_WORD(c15, c15, 0)}
383 	VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
407 	for (i = 0; i < VC4_KERNEL_DWORDS; i++) {  in vc4_hvs_upload_linear_kernel()
416 	return 0;  in vc4_hvs_upload_linear_kernel()
445 	for (i = 0; i < crtc->gamma_size; i++)  in vc4_hvs_lut_load()
447 	for (i = 0; i < crtc->gamma_size; i++)  in vc4_hvs_lut_load()
449 	for (i = 0; i < crtc->gamma_size; i++)  in vc4_hvs_lut_load()
464 	for (i = 0; i < length; i++) {  in vc4_hvs_update_gamma_lut()
477 	u8 field = 0;  in vc4_hvs_get_fifo_frame_count()
483 		return 0;  in vc4_hvs_get_fifo_frame_count()
493 		case 0:  in vc4_hvs_get_fifo_frame_count()
509 		case 0:  in vc4_hvs_get_fifo_frame_count()
553 		case 0:  in vc4_hvs_get_fifo_from_output()
554 			return 0;  in vc4_hvs_get_fifo_from_output()
562 			if (ret == 0)  in vc4_hvs_get_fifo_from_output()
565 			return 0;  in vc4_hvs_get_fifo_from_output()
598 		case 0:  in vc4_hvs_get_fifo_from_output()
599 			return 0;  in vc4_hvs_get_fifo_from_output()
636 	HVS_WRITE(SCALER_DISPCTRLX(chan), 0);  in vc4_hvs_init_channel()
638 	HVS_WRITE(SCALER_DISPCTRLX(chan), 0);  in vc4_hvs_init_channel()
653 			    (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);  in vc4_hvs_init_channel()
660 			    (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);  in vc4_hvs_init_channel()
670 		  ((vc4->gen == VC4_GEN_4) ? SCALER_DISPBKGND_GAMMA : 0) |  in vc4_hvs_init_channel()
671 		  (interlace ? SCALER_DISPBKGND_INTERLACE : 0));  in vc4_hvs_init_channel()
680 	return 0;  in vc4_hvs_init_channel()
704 		  disp_ctrl1 | (interlace ? SCALER6_DISPX_CTRL1_INTLACE : 0));  in vc6_hvs_init_channel()
710 		  (oneshot ? SCALER6_DISPX_CTRL0_ONESHOT : 0) |  in vc6_hvs_init_channel()
716 	return 0;  in vc6_hvs_init_channel()
734 	HVS_WRITE(SCALER_DISPCTRLX(chan), 0);  in __vc4_hvs_stop_channel()
798 	u32 dlist_count = 0;  in vc4_hvs_atomic_check()
831 	return 0;  in vc4_hvs_atomic_check()
866 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);  in vc4_hvs_update_dlist()
942 	unsigned int zpos = 0;  in vc4_hvs_atomic_flush()
1137 	for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {  in vc4_hvs_irq_handler()
1153 	HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |  in vc4_hvs_irq_handler()
1185 	return 0;  in vc4_hvs_debugfs_init()
1235 		for (i = 0; i < VC4_NUM_UPM_HANDLES; i++) {  in __vc4_hvs_alloc()
1236 			refcount_set(&hvs->upm_refcounts[i].refcount, 0);  in __vc4_hvs_alloc()
1282 	drm_mm_init(&hvs->lbm_mm, 0, lbm_size);  in __vc4_hvs_alloc()
1294 		drm_mm_init(&hvs->upm_mm, 0, 1024 * HVS_UBM_WORD_SIZE);  in __vc4_hvs_alloc()
1315 		  reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));  in vc4_hvs_hw_init()
1333 	dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |  in vc4_hvs_hw_init()
1341 			      SCALER_DISPCTRL_DSPEIEOF(0) |  in vc4_hvs_hw_init()
1344 			      SCALER_DISPCTRL_DSPEIEOLN(0) |  in vc4_hvs_hw_init()
1347 			      SCALER_DISPCTRL_DSPEISLUR(0) |  in vc4_hvs_hw_init()
1354 			      SCALER5_DISPCTRL_DSPEIEOF(0) |  in vc4_hvs_hw_init()
1357 			      SCALER5_DISPCTRL_DSPEIEOLN(0) |  in vc4_hvs_hw_init()
1360 			      SCALER5_DISPCTRL_DSPEISLUR(0) |  in vc4_hvs_hw_init()
1390 	return 0;  in vc4_hvs_hw_init()
1393 #define CFC1_N_NL_CSC_CTRL(x)		(0xa000 + ((x) * 0x3000))
1394 #define CFC1_N_MA_CSC_COEFF_C00(x)	(0xa008 + ((x) * 0x3000))
1395 #define CFC1_N_MA_CSC_COEFF_C01(x)	(0xa00c + ((x) * 0x3000))
1396 #define CFC1_N_MA_CSC_COEFF_C02(x)	(0xa010 + ((x) * 0x3000))
1397 #define CFC1_N_MA_CSC_COEFF_C03(x)	(0xa014 + ((x) * 0x3000))
1398 #define CFC1_N_MA_CSC_COEFF_C04(x)	(0xa018 + ((x) * 0x3000))
1399 #define CFC1_N_MA_CSC_COEFF_C10(x)	(0xa01c + ((x) * 0x3000))
1400 #define CFC1_N_MA_CSC_COEFF_C11(x)	(0xa020 + ((x) * 0x3000))
1401 #define CFC1_N_MA_CSC_COEFF_C12(x)	(0xa024 + ((x) * 0x3000))
1402 #define CFC1_N_MA_CSC_COEFF_C13(x)	(0xa028 + ((x) * 0x3000))
1403 #define CFC1_N_MA_CSC_COEFF_C14(x)	(0xa02c + ((x) * 0x3000))
1404 #define CFC1_N_MA_CSC_COEFF_C20(x)	(0xa030 + ((x) * 0x3000))
1405 #define CFC1_N_MA_CSC_COEFF_C21(x)	(0xa034 + ((x) * 0x3000))
1406 #define CFC1_N_MA_CSC_COEFF_C22(x)	(0xa038 + ((x) * 0x3000))
1407 #define CFC1_N_MA_CSC_COEFF_C23(x)	(0xa03c + ((x) * 0x3000))
1408 #define CFC1_N_MA_CSC_COEFF_C24(x)	(0xa040 + ((x) * 0x3000))
1410 #define SCALER_PI_CMP_CSC_RED0(x)		(0x200 + ((x) * 0x40))
1411 #define SCALER_PI_CMP_CSC_RED1(x)		(0x204 + ((x) * 0x40))
1412 #define SCALER_PI_CMP_CSC_RED_CLAMP(x)		(0x208 + ((x) * 0x40))
1413 #define SCALER_PI_CMP_CSC_CFG(x)		(0x20c + ((x) * 0x40))
1414 #define SCALER_PI_CMP_CSC_GREEN0(x)		(0x210 + ((x) * 0x40))
1415 #define SCALER_PI_CMP_CSC_GREEN1(x)		(0x214 + ((x) * 0x40))
1416 #define SCALER_PI_CMP_CSC_GREEN_CLAMP(x)	(0x218 + ((x) * 0x40))
1417 #define SCALER_PI_CMP_CSC_BLUE0(x)		(0x220 + ((x) * 0x40))
1418 #define SCALER_PI_CMP_CSC_BLUE1(x)		(0x224 + ((x) * 0x40))
1419 #define SCALER_PI_CMP_CSC_BLUE_CLAMP(x)		(0x228 + ((x) * 0x40))
1432 				{ 0x004A8542, 0x0, 0x0066254A, 0x0, 0xFF908A0D },
1433 				{ 0x004A8542, 0xFFE6ED5D, 0xFFCBF856, 0x0, 0x0043C9A3 },
1434 				{ 0x004A8542, 0x00811A54, 0x0, 0x0, 0xFF759502 }
1439 				{ 0x004A8542, 0x0, 0x0072BC44, 0x0, 0xFF83F312 },
1440 				{ 0x004A8542, 0xFFF25A22, 0xFFDDE4D0, 0x0, 0x00267064 },
1441 				{ 0x004A8542, 0x00873197, 0x0, 0x0, 0xFF6F7DC0 }
1446 				{ 0x004A8542, 0x0, 0x006B4A17, 0x0, 0xFF8B653F },
1447 				{ 0x004A8542, 0xFFF402D9, 0xFFDDE4D0, 0x0, 0x0024C7AE },
1448 				{ 0x004A8542, 0x008912CC, 0x0, 0x0, 0xFF6D9C8B }
1455 				{ 0x00400000, 0x0, 0x0059BA5E, 0x0, 0xFFA645A1 },
1456 				{ 0x00400000, 0xFFE9F9AC, 0xFFD24B97, 0x0, 0x0043BABB },
1457 				{ 0x00400000, 0x00716872, 0x0, 0x0, 0xFF8E978D }
1462 				{ 0x00400000, 0x0, 0x0064C985, 0x0, 0xFF9B367A },
1463 				{ 0x00400000, 0xFFF402E1, 0xFFE20A40, 0x0, 0x0029F2DE },
1464 				{ 0x00400000, 0x0076C226, 0x0, 0x0, 0xFF893DD9 }
1469 				{ 0x00400000, 0x0, 0x005E3F14, 0x0, 0xFFA1C0EB },
1470 				{ 0x00400000, 0xFFF577F6, 0xFFDB580F, 0x0, 0x002F2FFA },
1471 				{ 0x00400000, 0x007868DB, 0x0, 0x0, 0xFF879724 }
1488 	HVS_WRITE(SCALER6(PRI_MAP0), 0xffffffff);  in vc6_hvs_hw_init()
1489 	HVS_WRITE(SCALER6(PRI_MAP1), 0xffffffff);  in vc6_hvs_hw_init()
1492 		for (i = 0; i < 6; i++) {  in vc6_hvs_hw_init()
1495 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]);  in vc6_hvs_hw_init()
1496 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);  in vc6_hvs_hw_init()
1497 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]);  in vc6_hvs_hw_init()
1498 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]);  in vc6_hvs_hw_init()
1499 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]);  in vc6_hvs_hw_init()
1501 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);  in vc6_hvs_hw_init()
1507 			HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]);  in vc6_hvs_hw_init()
1516 		for (i = 0; i < 8; i++) {  in vc6_hvs_hw_init()
1517 			HVS_WRITE(SCALER_PI_CMP_CSC_RED0(i), 0x1f002566);  in vc6_hvs_hw_init()
1518 			HVS_WRITE(SCALER_PI_CMP_CSC_RED1(i), 0x3994);  in vc6_hvs_hw_init()
1519 			HVS_WRITE(SCALER_PI_CMP_CSC_RED_CLAMP(i), 0xfff00000);  in vc6_hvs_hw_init()
1520 			HVS_WRITE(SCALER_PI_CMP_CSC_CFG(i), 0x1);  in vc6_hvs_hw_init()
1521 			HVS_WRITE(SCALER_PI_CMP_CSC_GREEN0(i), 0x18002566);  in vc6_hvs_hw_init()
1522 			HVS_WRITE(SCALER_PI_CMP_CSC_GREEN1(i), 0xf927eee2);  in vc6_hvs_hw_init()
1523 			HVS_WRITE(SCALER_PI_CMP_CSC_GREEN_CLAMP(i), 0xfff00000);  in vc6_hvs_hw_init()
1524 			HVS_WRITE(SCALER_PI_CMP_CSC_BLUE0(i), 0x18002566);  in vc6_hvs_hw_init()
1525 			HVS_WRITE(SCALER_PI_CMP_CSC_BLUE1(i), 0x43d80000);  in vc6_hvs_hw_init()
1526 			HVS_WRITE(SCALER_PI_CMP_CSC_BLUE_CLAMP(i), 0xfff00000);  in vc6_hvs_hw_init()
1530 	return 0;  in vc6_hvs_hw_init()
1550 		 * channel 0.  in vc4_hvs_cob_init()
1555 		reg = 0;  in vc4_hvs_cob_init()
1576 		 * lines. to channel 0.  in vc4_hvs_cob_init()
1581 		reg = 0;  in vc4_hvs_cob_init()
1601 		base = 0;  in vc4_hvs_cob_init()
1618 		HVS_WRITE(SCALER6_DISPX_COB(0),  in vc4_hvs_cob_init()
1627 	return 0;  in vc4_hvs_cob_init()
1639 	regs = vc4_ioremap_regs(pdev, 0);  in vc4_hvs_bind()
1742 		ret = devm_request_irq(dev, platform_get_irq(pdev, 0),  in vc4_hvs_bind()
1743 				       vc4_hvs_irq_handler, 0, "vc4 hvs", drm);  in vc4_hvs_bind()
1748 	return 0;  in vc4_hvs_bind()