Lines Matching +full:4 +full:x12
14 #define VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB BIT(4)
20 #define VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN BIT(4)
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)
46 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)
54 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_SHIFT 4
55 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_MASK VC4_MASK(7, 4)
101 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_MASK VC4_MASK(5, 4)
102 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_SHIFT 4
119 #define VC4_HDMI_RM_CONTROL_FREE_RUN BIT(4)
131 #define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_RNDGEN_PWRUP BIT(4)
161 #define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING_MASK VC4_MASK(4, 3)
304 {{0x0, 0x0A}, 0x12, 0x0},
305 {{0x0, 0x0A}, 0x12, 0x0},
306 {{0x0, 0x0A}, 0x12, 0x0}
313 {{0x0, 0x09}, 0x12, 0x0},
314 {{0x0, 0x09}, 0x12, 0x0},
315 {{0x0, 0x09}, 0x12, 0x0}
322 {{0x0, 0x09}, 0x12, 0x0},
323 {{0x0, 0x09}, 0x12, 0x0},
324 {{0x0, 0x09}, 0x12, 0x0}
331 {{0x0, 0x0F}, 0x12, 0x1},
332 {{0x0, 0x0F}, 0x12, 0x1},
333 {{0x0, 0x0F}, 0x12, 0x1}
340 {{0x2, 0x0D}, 0x12, 0x1},
341 {{0x2, 0x0D}, 0x12, 0x1},
342 {{0x2, 0x0D}, 0x12, 0x1}
349 {{0x0, 0x1B}, 0x12, 0xF},
350 {{0x0, 0x1B}, 0x12, 0xF},
351 {{0x0, 0x1B}, 0x12, 0xF}
353 {{0x0, 0x0A}, 0x12, 0xF},
358 {{0x0, 0x1C}, 0x12, 0xF},
359 {{0x0, 0x1C}, 0x12, 0xF},
360 {{0x0, 0x1C}, 0x12, 0xF}
493 VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) | in vc5_hdmi_phy_init()
630 unsigned int ext_current_ctl:4;
641 unsigned int int_current_ctl:4;