Lines Matching refs:afec0
717 u32 afec0 = DSI_PORT_READ(PHY_AFEC0); in vc4_dsi_latch_ulps() local
720 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); in vc4_dsi_latch_ulps()
722 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); in vc4_dsi_latch_ulps()
724 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_latch_ulps()
944 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable() local
948 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; in vc4_dsi_bridge_pre_enable()
951 afec0 |= DSI0_PHY_AFEC0_RESET; in vc4_dsi_bridge_pre_enable()
953 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_bridge_pre_enable()
963 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable() local
972 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; in vc4_dsi_bridge_pre_enable()
974 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; in vc4_dsi_bridge_pre_enable()
976 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; in vc4_dsi_bridge_pre_enable()
978 afec0 |= DSI1_PHY_AFEC0_RESET; in vc4_dsi_bridge_pre_enable()
980 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_bridge_pre_enable()