661 #define DSI_PORT_WRITE(offset, val) \  macro
724 	DSI_PORT_WRITE(PHY_AFEC0, afec0);  in vc4_dsi_latch_ulps()
753 	DSI_PORT_WRITE(STAT, stat_ulps);  in vc4_dsi_ulps()
754 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);  in vc4_dsi_ulps()
760 		DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);  in vc4_dsi_ulps()
772 	DSI_PORT_WRITE(STAT, stat_stop);  in vc4_dsi_ulps()
773 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);  in vc4_dsi_ulps()
779 		DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);  in vc4_dsi_ulps()
810 	DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);  in vc4_dsi_bridge_disable()
931 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_bridge_pre_enable()
935 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_bridge_pre_enable()
940 	DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));  in vc4_dsi_bridge_pre_enable()
953 		DSI_PORT_WRITE(PHY_AFEC0, afec0);  in vc4_dsi_bridge_pre_enable()
958 		DSI_PORT_WRITE(PHY_AFEC1,  in vc4_dsi_bridge_pre_enable()
980 		DSI_PORT_WRITE(PHY_AFEC0, afec0);  in vc4_dsi_bridge_pre_enable()
982 		DSI_PORT_WRITE(PHY_AFEC1, 0);  in vc4_dsi_bridge_pre_enable()
1028 	DSI_PORT_WRITE(HS_CLT0,  in vc4_dsi_bridge_pre_enable()
1036 	DSI_PORT_WRITE(HS_CLT1,  in vc4_dsi_bridge_pre_enable()
1042 	DSI_PORT_WRITE(HS_CLT2,  in vc4_dsi_bridge_pre_enable()
1046 	DSI_PORT_WRITE(HS_DLT3,  in vc4_dsi_bridge_pre_enable()
1054 	DSI_PORT_WRITE(HS_DLT4,  in vc4_dsi_bridge_pre_enable()
1071 	DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,  in vc4_dsi_bridge_pre_enable()
1075 	DSI_PORT_WRITE(HS_DLT6,  in vc4_dsi_bridge_pre_enable()
1081 	DSI_PORT_WRITE(HS_DLT7,  in vc4_dsi_bridge_pre_enable()
1085 	DSI_PORT_WRITE(PHYC,  in vc4_dsi_bridge_pre_enable()
1097 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_bridge_pre_enable()
1102 	DSI_PORT_WRITE(HSTX_TO_CNT, 0);  in vc4_dsi_bridge_pre_enable()
1104 	DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);  in vc4_dsi_bridge_pre_enable()
1106 	DSI_PORT_WRITE(TA_TO_CNT, 100000);  in vc4_dsi_bridge_pre_enable()
1108 	DSI_PORT_WRITE(PR_TO_CNT, 100000);  in vc4_dsi_bridge_pre_enable()
1113 	DSI_PORT_WRITE(DISP1_CTRL,  in vc4_dsi_bridge_pre_enable()
1120 		DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);  in vc4_dsi_bridge_pre_enable()
1122 		DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);  in vc4_dsi_bridge_pre_enable()
1125 	DSI_PORT_WRITE(PHY_AFEC0,  in vc4_dsi_bridge_pre_enable()
1132 		DSI_PORT_WRITE(DISP0_CTRL,  in vc4_dsi_bridge_pre_enable()
1140 		DSI_PORT_WRITE(DISP0_CTRL,  in vc4_dsi_bridge_pre_enable()
1154 	DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);  in vc4_dsi_bridge_enable()
1224 		DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);  in vc4_dsi_host_transfer()
1228 		DSI_PORT_WRITE(TXPKT_PIX_FIFO,  in vc4_dsi_host_transfer()
1258 		DSI_PORT_WRITE(INT_STAT,  in vc4_dsi_host_transfer()
1261 			DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |  in vc4_dsi_host_transfer()
1264 			DSI_PORT_WRITE(INT_EN,  in vc4_dsi_host_transfer()
1270 		DSI_PORT_WRITE(INT_STAT,  in vc4_dsi_host_transfer()
1273 			DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |  in vc4_dsi_host_transfer()
1276 			DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |  in vc4_dsi_host_transfer()
1282 	DSI_PORT_WRITE(TXPKT1H, pkth);  in vc4_dsi_host_transfer()
1283 	DSI_PORT_WRITE(TXPKT1C, pktc);  in vc4_dsi_host_transfer()
1295 	DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));  in vc4_dsi_host_transfer()
1334 	DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);  in vc4_dsi_host_transfer()
1336 	DSI_PORT_WRITE(CTRL,  in vc4_dsi_host_transfer()
1340 	DSI_PORT_WRITE(TXPKT1C, 0);  in vc4_dsi_host_transfer()
1341 	DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));  in vc4_dsi_host_transfer()
1506 	DSI_PORT_WRITE(INT_STAT, stat);  in vc4_dsi_irq_handler()
1728 	DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);  in vc4_dsi_bind()
1730 	DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));  in vc4_dsi_bind()