Lines Matching +full:12 +full:bit +full:- +full:clk +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0-only
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
16 * This driver has been tested for DSI1 video-mode display only
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
88 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90 # define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91 # define DSI_TXPKT1C_CMD_EN BIT(0)
105 # define DSI_RXPKT1H_CRC_ERR BIT(31)
106 # define DSI_RXPKT1H_DET_ERR BIT(30)
107 # define DSI_RXPKT1H_ECC_ERR BIT(29)
108 # define DSI_RXPKT1H_COR_ERR BIT(28)
109 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
124 # define DSI_RXPKT1H_DET_ERR BIT(30)
125 # define DSI_RXPKT1H_ECC_ERR BIT(29)
126 # define DSI_RXPKT1H_COR_ERR BIT(28)
127 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
139 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
146 * of going to LP-STOP.
148 # define DSI_DISP_HACTIVE_NULL BIT(10)
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150 # define DSI_DISP_VBLP_CTRL BIT(9)
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152 # define DSI_DISP_HFP_CTRL BIT(8)
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154 # define DSI_DISP_HBP_CTRL BIT(7)
158 # define DSI_DISP0_ST_END BIT(4)
166 # define DSI_DISP0_COMMAND_MODE BIT(1)
167 # define DSI_DISP0_ENABLE BIT(0)
180 # define DSI_DISP1_ENABLE BIT(0)
186 # define DSI0_INT_FIFO_ERR BIT(25)
191 # define DSI0_INT_PHY_DIR_RTF BIT(22)
192 # define DSI0_INT_PHY_D1_ULPS BIT(21)
193 # define DSI0_INT_PHY_D1_STOP BIT(20)
194 # define DSI0_INT_PHY_RXLPDT BIT(19)
195 # define DSI0_INT_PHY_RXTRIG BIT(18)
196 # define DSI0_INT_PHY_D0_ULPS BIT(17)
197 # define DSI0_INT_PHY_D0_LPDT BIT(16)
198 # define DSI0_INT_PHY_D0_FTR BIT(15)
199 # define DSI0_INT_PHY_D0_STOP BIT(14)
201 # define DSI0_INT_PHY_CLK_ULPS BIT(13)
202 # define DSI0_INT_PHY_CLK_HS BIT(12)
203 # define DSI0_INT_PHY_CLK_FTR BIT(11)
205 # define DSI0_INT_PR_TO BIT(10)
206 # define DSI0_INT_TA_TO BIT(9)
207 # define DSI0_INT_LPRX_TO BIT(8)
208 # define DSI0_INT_HSTX_TO BIT(7)
210 # define DSI0_INT_ERR_CONT_LP1 BIT(6)
211 # define DSI0_INT_ERR_CONT_LP0 BIT(5)
213 # define DSI0_INT_ERR_CONTROL BIT(4)
214 # define DSI0_INT_ERR_SYNC_ESC BIT(3)
215 # define DSI0_INT_RX2_PKT BIT(2)
216 # define DSI0_INT_RX1_PKT BIT(1)
217 # define DSI0_INT_CMD_PKT BIT(0)
228 # define DSI1_INT_PHY_D3_ULPS BIT(30)
229 # define DSI1_INT_PHY_D3_STOP BIT(29)
230 # define DSI1_INT_PHY_D2_ULPS BIT(28)
231 # define DSI1_INT_PHY_D2_STOP BIT(27)
232 # define DSI1_INT_PHY_D1_ULPS BIT(26)
233 # define DSI1_INT_PHY_D1_STOP BIT(25)
234 # define DSI1_INT_PHY_D0_ULPS BIT(24)
235 # define DSI1_INT_PHY_D0_STOP BIT(23)
236 # define DSI1_INT_FIFO_ERR BIT(22)
237 # define DSI1_INT_PHY_DIR_RTF BIT(21)
238 # define DSI1_INT_PHY_RXLPDT BIT(20)
239 # define DSI1_INT_PHY_RXTRIG BIT(19)
240 # define DSI1_INT_PHY_D0_LPDT BIT(18)
241 # define DSI1_INT_PHY_DIR_FTR BIT(17)
244 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
245 # define DSI1_INT_PHY_CLOCK_HS BIT(15)
246 # define DSI1_INT_PHY_CLOCK_STOP BIT(14)
249 # define DSI1_INT_PR_TO BIT(13)
250 # define DSI1_INT_TA_TO BIT(12)
251 # define DSI1_INT_LPRX_TO BIT(11)
252 # define DSI1_INT_HSTX_TO BIT(10)
255 # define DSI1_INT_ERR_CONT_LP1 BIT(9)
256 # define DSI1_INT_ERR_CONT_LP0 BIT(8)
259 # define DSI1_INT_ERR_CONTROL BIT(7)
262 # define DSI1_INT_ERR_SYNC_ESC BIT(6)
266 # define DSI1_INT_RXPKT2 BIT(5)
271 # define DSI1_INT_RXPKT1 BIT(4)
272 # define DSI1_INT_TXPKT2_DONE BIT(3)
273 # define DSI1_INT_TXPKT2_END BIT(2)
275 # define DSI1_INT_TXPKT1_DONE BIT(1)
277 # define DSI1_INT_TXPKT1_END BIT(0)
296 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
297 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
298 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
299 # define DSI1_PHYC_CLANE_ULPS BIT(17)
300 # define DSI1_PHYC_CLANE_ENABLE BIT(16)
301 # define DSI_PHYC_DLANE3_ULPS BIT(13)
302 # define DSI_PHYC_DLANE3_ENABLE BIT(12)
303 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
304 # define DSI0_PHYC_CLANE_ULPS BIT(9)
305 # define DSI_PHYC_DLANE2_ULPS BIT(9)
306 # define DSI0_PHYC_CLANE_ENABLE BIT(8)
307 # define DSI_PHYC_DLANE2_ENABLE BIT(8)
308 # define DSI_PHYC_DLANE1_ULPS BIT(5)
309 # define DSI_PHYC_DLANE1_ENABLE BIT(4)
310 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
311 # define DSI_PHYC_DLANE0_ULPS BIT(1)
312 # define DSI_PHYC_DLANE0_ENABLE BIT(0)
324 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
325 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
326 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
341 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
342 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
343 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
344 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
345 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
346 # define DSI1_PHY_AFEC0_RESET BIT(13)
347 # define DSI1_PHY_AFEC0_PD BIT(12)
348 # define DSI0_PHY_AFEC0_RESET BIT(11)
349 # define DSI1_PHY_AFEC0_PD_BG BIT(11)
350 # define DSI0_PHY_AFEC0_PD BIT(10)
351 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
352 # define DSI0_PHY_AFEC0_PD_BG BIT(9)
353 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
354 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
355 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
381 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
382 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
383 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
384 # define DSI_CTRL_SOFT_RESET_CFG BIT(10)
385 # define DSI_CTRL_CAL_BYTE BIT(9)
386 # define DSI_CTRL_INV_BYTE BIT(8)
387 # define DSI_CTRL_CLR_LDF BIT(7)
388 # define DSI0_CTRL_CLR_PBCF BIT(6)
389 # define DSI1_CTRL_CLR_RXF BIT(6)
390 # define DSI0_CTRL_CLR_CPBCF BIT(5)
391 # define DSI1_CTRL_CLR_PDF BIT(5)
392 # define DSI0_CTRL_CLR_PDF BIT(4)
393 # define DSI1_CTRL_CLR_CDF BIT(4)
394 # define DSI0_CTRL_CLR_CDF BIT(3)
395 # define DSI0_CTRL_CTRL2 BIT(2)
396 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
397 # define DSI0_CTRL_CTRL1 BIT(1)
398 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
399 # define DSI0_CTRL_CTRL0 BIT(0)
400 # define DSI1_CTRL_EN BIT(0)
419 * writing a 1 clears the bit.
422 # define DSI1_STAT_PHY_D3_ULPS BIT(31)
423 # define DSI1_STAT_PHY_D3_STOP BIT(30)
424 # define DSI1_STAT_PHY_D2_ULPS BIT(29)
425 # define DSI1_STAT_PHY_D2_STOP BIT(28)
426 # define DSI1_STAT_PHY_D1_ULPS BIT(27)
427 # define DSI1_STAT_PHY_D1_STOP BIT(26)
428 # define DSI1_STAT_PHY_D0_ULPS BIT(25)
429 # define DSI1_STAT_PHY_D0_STOP BIT(24)
430 # define DSI1_STAT_FIFO_ERR BIT(23)
431 # define DSI1_STAT_PHY_RXLPDT BIT(22)
432 # define DSI1_STAT_PHY_RXTRIG BIT(21)
433 # define DSI1_STAT_PHY_D0_LPDT BIT(20)
435 # define DSI1_STAT_PHY_DIR BIT(19)
436 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
437 # define DSI1_STAT_PHY_CLOCK_HS BIT(17)
438 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
439 # define DSI1_STAT_PR_TO BIT(15)
440 # define DSI1_STAT_TA_TO BIT(14)
441 # define DSI1_STAT_LPRX_TO BIT(13)
442 # define DSI1_STAT_HSTX_TO BIT(12)
443 # define DSI1_STAT_ERR_CONT_LP1 BIT(11)
444 # define DSI1_STAT_ERR_CONT_LP0 BIT(10)
445 # define DSI1_STAT_ERR_CONTROL BIT(9)
446 # define DSI1_STAT_ERR_SYNC_ESC BIT(8)
447 # define DSI1_STAT_RXPKT2 BIT(7)
448 # define DSI1_STAT_RXPKT1 BIT(6)
449 # define DSI1_STAT_TXPKT2_BUSY BIT(5)
450 # define DSI1_STAT_TXPKT2_DONE BIT(4)
451 # define DSI1_STAT_TXPKT2_END BIT(3)
452 # define DSI1_STAT_TXPKT1_BUSY BIT(2)
453 # define DSI1_STAT_TXPKT1_DONE BIT(1)
454 # define DSI1_STAT_TXPKT1_END BIT(0)
519 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
520 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
573 u32 divider;
579 struct clk *escape_clock;
581 /* Input clock to the analog PHY, used to generate the DSI bit
584 struct clk *pll_phy_clock;
594 struct clk *pixel_clock;
614 struct drm_device *drm = dsi->bridge.dev;
615 struct dma_chan *chan = dsi->reg_dma_chan;
624 writel(val, dsi->regs + offset);
628 *dsi->reg_dma_mem = val;
630 tx = chan->device->device_prep_dma_memcpy(chan,
631 dsi->reg_paddr + offset,
632 dsi->reg_dma_paddr,
639 cookie = tx->tx_submit(tx);
653 readl(dsi->regs + (offset)); \
658 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
660 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
661 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
728 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
731 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
732 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
733 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
736 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
737 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
738 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
741 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
742 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
743 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
755 dev_warn(&dsi->pdev->dev,
774 dev_warn(&dsi->pdev->dev,
815 struct device *dev = &dsi->pdev->dev;
817 clk_disable_unprepare(dsi->pll_phy_clock);
818 clk_disable_unprepare(dsi->escape_clock);
819 clk_disable_unprepare(dsi->pixel_clock);
824 /* Extends the mode's blank intervals to handle BCM2835's integer-only
825 * DSI PLL divider.
829 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
830 * the pixel clock), only has an integer divider off of DSI.
834 * higher-than-expected clock rate to the panel, but that's what the
842 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
844 unsigned long pixel_clock_hz = mode->clock * 1000;
845 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
846 int divider;
848 /* Find what divider gets us a faster clock than the requested
851 for (divider = 1; divider < 255; divider++) {
852 if (parent_rate / (divider + 1) < pll_clock)
856 /* Now that we've picked a PLL divider, calculate back to its
859 pll_clock = parent_rate / divider;
860 pixel_clock_hz = pll_clock / dsi->divider;
862 adjusted_mode->clock = pixel_clock_hz / 1000;
865 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
866 mode->clock;
867 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
868 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
878 struct device *dev = &dsi->pdev->dev;
894 drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
899 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
900 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
901 drm_print_regset32(&p, &dsi->regset);
909 bridge->encoder);
910 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
912 mode = &crtc_state->adjusted_mode;
914 pixel_clock_hz = mode->clock * 1000;
917 * PLLD_DSI1 is an integer divider and its rate selection will
920 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
921 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
923 dev_err(&dsi->pdev->dev,
940 if (dsi->variant->port == 0) {
944 if (dsi->lanes < 2)
947 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
968 if (dsi->lanes < 4)
970 if (dsi->lanes < 3)
972 if (dsi->lanes < 2)
985 ret = clk_prepare_enable(dsi->escape_clock);
987 drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n",
992 ret = clk_prepare_enable(dsi->pll_phy_clock);
994 drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret);
998 hs_clock = clk_get_rate(dsi->pll_phy_clock);
1008 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
1014 ret = clk_prepare_enable(dsi->pixel_clock);
1016 drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret);
1059 /* T_INIT is how long STOP is driven after power-up to
1060 * indicate to the slave (also coming out of power-up) that
1063 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1084 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1085 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1086 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1088 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1090 (dsi->variant->port == 0 ?
1091 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1092 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1116 if (dsi->variant->port == 0)
1128 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1130 VC4_SET_FIELD(dsi->divider,
1132 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1154 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1155 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1156 drm_print_regset32(&p, &dsi->regset);
1167 return drm_bridge_attach(encoder, dsi->out_bridge,
1168 &dsi->bridge, flags);
1175 struct drm_device *drm = dsi->bridge.dev;
1179 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1190 * The command FIFO takes byte-oriented data, but is of
1204 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1213 if (msg->rx_len) {
1233 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1253 dsi->xfer_result = 0;
1254 reinit_completion(&dsi->xfer_completion);
1255 if (dsi->variant->port == 0) {
1258 if (msg->rx_len) {
1270 if (msg->rx_len) {
1283 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1285 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1286 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1288 ret = -ETIMEDOUT;
1290 ret = dsi->xfer_result;
1298 if (ret == 0 && msg->rx_len) {
1300 u8 *msg_rx = msg->rx_buf;
1306 if (rxlen != msg->rx_len) {
1308 rxlen, (int)msg->rx_len);
1309 ret = -ENXIO;
1313 for (i = 0; i < msg->rx_len; i++)
1320 if (msg->rx_len > 1) {
1350 dsi->lanes = device->lanes;
1351 dsi->channel = device->channel;
1352 dsi->mode_flags = device->mode_flags;
1354 switch (device->format) {
1356 dsi->format = DSI_PFORMAT_RGB888;
1357 dsi->divider = 24 / dsi->lanes;
1360 dsi->format = DSI_PFORMAT_RGB666;
1361 dsi->divider = 24 / dsi->lanes;
1364 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1365 dsi->divider = 18 / dsi->lanes;
1368 dsi->format = DSI_PFORMAT_RGB565;
1369 dsi->divider = 16 / dsi->lanes;
1372 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1373 dsi->format);
1377 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1378 dev_err(&dsi->pdev->dev,
1383 drm_bridge_add(&dsi->bridge);
1385 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1387 drm_bridge_remove(&dsi->bridge);
1399 component_del(&dsi->pdev->dev, &vc4_dsi_ops);
1400 drm_bridge_remove(&dsi->bridge);
1424 struct drm_device *drm = encoder->dev;
1427 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset);
1459 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1460 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1461 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1466 irqreturn_t *ret, u32 stat, u32 bit,
1469 if (!(stat & bit))
1472 drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port,
1523 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1526 complete(&dsi->xfer_completion);
1529 complete(&dsi->xfer_completion);
1530 dsi->xfer_result = -ETIMEDOUT;
1538 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1539 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1545 struct device *dev = &dsi->pdev->dev;
1546 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1557 dsi->clk_onecell = devm_kzalloc(dev,
1558 sizeof(*dsi->clk_onecell) +
1562 if (!dsi->clk_onecell)
1563 return -ENOMEM;
1564 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1567 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1573 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1584 fix->mult = 1;
1585 fix->div = phy_clocks[i].div;
1586 fix->hw.init = &init;
1594 ret = devm_clk_hw_register(dev, &fix->hw);
1598 dsi->clk_onecell->hws[i] = &fix->hw;
1601 return of_clk_add_hw_provider(dev->of_node,
1603 dsi->clk_onecell);
1609 struct device *dev = &dsi->pdev->dev;
1611 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr);
1612 dsi->reg_dma_mem = NULL;
1619 dma_release_channel(dsi->reg_dma_chan);
1620 dsi->reg_dma_chan = NULL;
1627 drm_bridge_put(&dsi->bridge);
1635 struct drm_encoder *encoder = &dsi->encoder.base;
1638 drm_bridge_get(&dsi->bridge);
1644 dsi->variant = of_device_get_match_data(dev);
1646 dsi->encoder.type = dsi->variant->port ?
1649 dsi->regs = vc4_ioremap_regs(pdev, 0);
1650 if (IS_ERR(dsi->regs))
1651 return PTR_ERR(dsi->regs);
1653 dsi->regset.base = dsi->regs;
1654 dsi->regset.regs = dsi->variant->regs;
1655 dsi->regset.nregs = dsi->variant->nregs;
1660 return -ENODEV;
1667 if (dsi->variant->broken_axi_workaround) {
1670 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1671 &dsi->reg_dma_paddr,
1673 if (!dsi->reg_dma_mem) {
1675 return -ENOMEM;
1685 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1686 if (IS_ERR(dsi->reg_dma_chan)) {
1687 ret = PTR_ERR(dsi->reg_dma_chan);
1688 if (ret != -EPROBE_DEFER)
1702 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1706 init_completion(&dsi->xfer_completion);
1707 /* At startup enable error-reporting interrupts and nothing else. */
1712 if (dsi->reg_dma_mem)
1722 if (ret != -EPROBE_DEFER)
1727 dsi->escape_clock = devm_clk_get(dev, "escape");
1728 if (IS_ERR(dsi->escape_clock)) {
1729 ret = PTR_ERR(dsi->escape_clock);
1730 if (ret != -EPROBE_DEFER)
1735 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1736 if (IS_ERR(dsi->pll_phy_clock)) {
1737 ret = PTR_ERR(dsi->pll_phy_clock);
1738 if (ret != -EPROBE_DEFER)
1743 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1744 if (IS_ERR(dsi->pixel_clock)) {
1745 ret = PTR_ERR(dsi->pixel_clock);
1746 if (ret != -EPROBE_DEFER)
1751 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0);
1752 if (IS_ERR(dsi->out_bridge))
1753 return PTR_ERR(dsi->out_bridge);
1756 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1777 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1790 struct device *dev = &pdev->dev;
1793 dsi = devm_drm_bridge_alloc(&pdev->dev, struct vc4_dsi, bridge, &vc4_dsi_bridge_funcs);
1798 dsi->pdev = pdev;
1800 dsi->bridge.of_node = dev->of_node;
1802 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1803 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1804 dsi->dsi_host.dev = dev;
1805 mipi_dsi_host_register(&dsi->dsi_host);
1812 struct device *dev = &pdev->dev;
1815 mipi_dsi_host_unregister(&dsi->dsi_host);