Lines Matching +full:bcm2835 +full:- +full:vc4
1 // SPDX-License-Identifier: GPL-2.0-only
7 * DOC: VC4 CRTC module
9 * In VC4, the Pixel Valve is what most closely corresponds to the
27 * output-specific clock. Since the encoders also directly consume
57 writel(val, vc4_crtc->regs + (offset)); \
63 readl(vc4_crtc->regs + (offset)); \
83 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
85 struct vc4_hvs *hvs = vc4->hvs;
88 /* Top/base are supposed to be 4-pixel aligned, but the
93 if (vc4->gen >= VC4_GEN_6_C) {
103 return top - base + 4;
112 struct drm_device *dev = crtc->dev;
113 struct vc4_dev *vc4 = to_vc4_dev(dev);
114 struct vc4_hvs *hvs = vc4->hvs;
116 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
117 unsigned int channel = vc4_crtc_state->assigned_channel;
134 if (vc4->gen >= VC4_GEN_6_C)
147 if (vc4->gen >= VC4_GEN_6_C)
154 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
159 *hpos += mode->crtc_htotal / 2;
162 cob_size = vc4_crtc_get_cob_allocation(vc4, channel);
163 /* This is the offset we need for translating hvs -> pv scanout pos. */
164 fifo_lines = cob_size / mode->crtc_hdisplay;
179 * incrementing vpos. Therefore we choose HVS read position -
183 *vpos -= fifo_lines + 1;
191 * fifo with new lines from the top-most lines of the new framebuffers.
197 vblank_lines = mode->vtotal - mode->vdisplay;
209 *vpos = -vblank_lines;
212 *stime = vc4_crtc->t_vblank;
214 *etime = vc4_crtc->t_vblank;
242 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
248 u32 fifo_len_bytes = pv_data->fifo_depth;
263 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
265 return fifo_len_bytes - 14;
273 if (crtc_data->hvs_output == 5)
289 if (vc4->gen == VC4_GEN_4)
290 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
292 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
312 * VC4 can only scan out to one encoder at a time, while the DRM core
321 WARN_ON(hweight32(state->encoder_mask) > 1);
323 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
332 struct drm_device *dev = crtc->dev;
348 struct drm_device *dev = crtc->dev;
349 struct vc4_dev *vc4 = to_vc4_dev(dev);
353 struct drm_crtc_state *crtc_state = crtc->state;
354 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
355 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
356 bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||
357 vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;
358 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;
359 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
360 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
361 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
362 bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
364 u8 ppc = pv_data->pixels_per_clock;
366 u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
367 u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
368 u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;
377 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
378 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
380 drm_print_regset32(&p, &vc4_crtc->regset);
386 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
388 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
392 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
394 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
399 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc);
406 if (mode->htotal == 858) {
407 /* 525-line mode (NTSC or PAL-M) */
422 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
429 (vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |
441 (vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |
451 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
454 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
456 if (vc4->gen >= VC4_GEN_5)
461 if (vc4->gen >= VC4_GEN_6_C)
470 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
474 VC4_SET_FIELD(vc4_encoder->clock_select,
478 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
479 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
481 drm_print_regset32(&p, &vc4_crtc->regset);
489 struct vc4_dev *vc4 = to_vc4_dev(dev);
490 struct vc4_hvs *hvs = vc4->hvs;
492 if (vc4->gen >= VC4_GEN_6_C)
505 struct drm_device *dev = crtc->dev;
506 struct vc4_dev *vc4 = to_vc4_dev(dev);
510 return -ENODEV;
535 if (vc4_encoder && vc4_encoder->post_crtc_disable)
536 vc4_encoder->post_crtc_disable(encoder, state);
539 vc4_hvs_stop_channel(vc4->hvs, channel);
541 if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
542 vc4_encoder->post_crtc_powerdown(encoder, state);
551 struct drm_device *drm = crtc->dev;
552 struct vc4_dev *vc4 = to_vc4_dev(drm);
562 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
563 "brcm,bcm2711-pixelvalve2") ||
564 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
565 "brcm,bcm2711-pixelvalve4") ||
566 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
567 "brcm,bcm2712-pixelvalve0") ||
568 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
569 "brcm,bcm2712-pixelvalve1")))
578 channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
587 encoder_type = pv_data->encoder_types[encoder_sel];
593 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
612 struct drm_device *dev = crtc->dev;
615 if (!crtc->state || !crtc->state->event)
618 spin_lock_irqsave(&dev->event_lock, flags);
619 drm_crtc_send_vblank_event(crtc, crtc->state->event);
620 crtc->state->event = NULL;
621 spin_unlock_irqrestore(&dev->event_lock, flags);
631 struct drm_device *dev = crtc->dev;
634 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
641 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
655 struct drm_device *dev = crtc->dev;
662 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
676 if (vc4_encoder->pre_crtc_configure)
677 vc4_encoder->pre_crtc_configure(encoder, state);
683 if (vc4_encoder->pre_crtc_enable)
684 vc4_encoder->pre_crtc_enable(encoder, state);
692 if (vc4_encoder->post_crtc_enable)
693 vc4_encoder->post_crtc_enable(encoder, state);
702 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
704 crtc->base.id);
720 *left = vc4_state->margins.left;
721 *right = vc4_state->margins.right;
722 *top = vc4_state->margins.top;
723 *bottom = vc4_state->margins.bottom;
730 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
731 if (conn_state->crtc != state->crtc)
734 *left = conn_state->tv.margins.left;
735 *right = conn_state->tv.margins.right;
736 *top = conn_state->tv.margins.top;
737 *bottom = conn_state->tv.margins.bottom;
759 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
762 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
763 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000,
764 mode->clock * 9 / 10) * 1000;
766 vc4_state->hvs_load = mode->clock * 1000;
772 if (conn_state->crtc != crtc)
775 if (memcmp(&vc4_state->margins, &conn_state->tv.margins,
776 sizeof(vc4_state->margins))) {
777 memcpy(&vc4_state->margins, &conn_state->tv.margins,
778 sizeof(vc4_state->margins));
784 crtc_state->zpos_changed = true;
795 struct drm_device *dev = crtc->dev;
799 return -ENODEV;
811 struct drm_device *dev = crtc->dev;
824 struct drm_crtc *crtc = &vc4_crtc->base;
825 struct drm_device *dev = crtc->dev;
826 struct vc4_dev *vc4 = to_vc4_dev(dev);
827 struct vc4_hvs *hvs = vc4->hvs;
829 u32 chan = vc4_crtc->current_hvs_channel;
832 spin_lock_irqsave(&dev->event_lock, flags);
833 spin_lock(&vc4_crtc->irq_lock);
835 if (vc4->gen >= VC4_GEN_6_C)
841 if (vc4_crtc->event &&
842 (vc4_crtc->current_dlist == current_dlist || vc4_crtc->feeds_txp)) {
843 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
844 vc4_crtc->event = NULL;
853 if (vc4->gen < VC4_GEN_6_C)
856 spin_unlock(&vc4_crtc->irq_lock);
857 spin_unlock_irqrestore(&dev->event_lock, flags);
862 crtc->t_vblank = ktime_get();
863 drm_crtc_handle_vblank(&crtc->base);
896 struct drm_crtc *crtc = flip_state->crtc;
897 struct drm_device *dev = crtc->dev;
898 struct drm_plane *plane = crtc->primary;
900 vc4_plane_async_set_fb(plane, flip_state->fb);
901 if (flip_state->event) {
904 spin_lock_irqsave(&dev->event_lock, flags);
905 drm_crtc_send_vblank_event(crtc, flip_state->event);
906 spin_unlock_irqrestore(&dev->event_lock, flags);
910 drm_framebuffer_put(flip_state->fb);
912 if (flip_state->old_fb)
913 drm_framebuffer_put(flip_state->old_fb);
925 if (flip_state->old_fb) {
927 drm_fb_dma_get_gem_obj(flip_state->old_fb, 0);
928 bo = to_vc4_bo(&dma_bo->base);
939 * FIXME: we should move to generic async-page-flip when
941 * hand-made cleanup_fb() logic.
960 struct drm_framebuffer *fb = flip_state->fb;
963 struct vc4_dev *vc4 = to_vc4_dev(dev);
967 if (vc4->gen == VC4_GEN_4)
972 ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
978 async_page_flip_complete_function(fence, &flip_state->cb);
983 if (dma_fence_add_callback(fence, &flip_state->cb,
985 async_page_flip_complete_function(fence, &flip_state->cb);
996 struct drm_device *dev = crtc->dev;
997 struct drm_plane *plane = crtc->primary;
1002 return -ENOMEM;
1005 flip_state->fb = fb;
1006 flip_state->crtc = crtc;
1007 flip_state->event = event;
1013 * FIXME: we should move to generic async-page-flip when it's
1014 * available, so that we can get rid of this hand-made cleanup_fb()
1017 flip_state->old_fb = plane->state->fb;
1018 if (flip_state->old_fb)
1019 drm_framebuffer_get(flip_state->old_fb);
1027 drm_atomic_set_fb_for_plane(plane->state, fb);
1035 /* Implements async (non-vblank-synced) page flips.
1046 struct drm_device *dev = crtc->dev;
1047 struct vc4_dev *vc4 = to_vc4_dev(dev);
1049 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
1052 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
1053 return -ENODEV;
1058 * plane is later updated through the non-async path.
1060 * FIXME: we should move to generic async-page-flip when
1062 * hand-made prepare_fb() logic.
1092 struct drm_device *dev = crtc->dev;
1093 struct vc4_dev *vc4 = to_vc4_dev(dev);
1095 if (vc4->gen > VC4_GEN_4)
1112 old_vc4_state = to_vc4_crtc_state(crtc->state);
1113 vc4_state->margins = old_vc4_state->margins;
1114 vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1116 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1117 return &vc4_state->base;
1123 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1126 if (drm_mm_node_allocated(&vc4_state->mm)) {
1129 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1130 drm_mm_remove_node(&vc4_state->mm);
1131 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1142 if (crtc->state)
1143 vc4_crtc_destroy_state(crtc, crtc->state);
1147 crtc->state = NULL;
1151 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1152 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1157 struct drm_device *drm = crtc->dev;
1161 vc4_debugfs_add_regset32(drm, crtc_data->debugfs_name,
1162 &vc4_crtc->regset);
1194 .name = "pixelvalve-0",
1209 .name = "pixelvalve-1",
1224 .name = "pixelvalve-2",
1239 .name = "pixelvalve-0",
1254 .name = "pixelvalve-1",
1269 .name = "pixelvalve-2",
1283 .name = "pixelvalve-3",
1297 .name = "pixelvalve-4",
1336 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1337 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1338 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1339 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1340 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1341 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1342 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1343 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1344 { .compatible = "brcm,bcm2712-pixelvalve0", .data = &bcm2712_pv0_data },
1345 { .compatible = "brcm,bcm2712-pixelvalve1", .data = &bcm2712_pv1_data },
1354 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1361 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1365 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1366 if (vc4_encoder->type == encoder_types[i]) {
1367 vc4_encoder->clock_select = i;
1368 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1376 * __vc4_crtc_init - Initializes a CRTC
1402 struct vc4_dev *vc4 = to_vc4_dev(drm);
1403 struct drm_crtc *crtc = &vc4_crtc->base;
1407 vc4_crtc->data = data;
1408 vc4_crtc->pdev = pdev;
1409 vc4_crtc->feeds_txp = feeds_txp;
1410 spin_lock_init(&vc4_crtc->irq_lock);
1412 crtc_funcs, data->name);
1418 if (vc4->gen == VC4_GEN_4) {
1419 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1420 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1425 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1428 for (i = 0; i < crtc->gamma_size; i++) {
1429 vc4_crtc->lut_r[i] = i;
1430 vc4_crtc->lut_g[i] = i;
1431 vc4_crtc->lut_b[i] = i;
1454 dev_err(drm->dev, "failed to construct primary plane\n");
1473 return -ENOMEM;
1474 crtc = &vc4_crtc->base;
1478 return -ENODEV;
1480 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1481 if (IS_ERR(vc4_crtc->regs))
1482 return PTR_ERR(vc4_crtc->regs);
1484 vc4_crtc->regset.base = vc4_crtc->regs;
1485 vc4_crtc->regset.regs = crtc_regs;
1486 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1488 ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base,
1500 "vc4 crtc", vc4_crtc);
1527 return component_add(&pdev->dev, &vc4_crtc_ops);
1532 component_del(&pdev->dev, &vc4_crtc_ops);