1 // SPDX-License-Identifier: GPL-2.0-only
21  * image domain can feed either HDMI or the SDTV controller.  The
22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
27  * output-specific clock.  Since the encoders also directly consume
57 		writel(val, vc4_crtc->regs + (offset));					\
63 		readl(vc4_crtc->regs + (offset));					\
85 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_crtc_get_cob_allocation()
88 	/* Top/base are supposed to be 4-pixel aligned, but the  in vc4_crtc_get_cob_allocation()
93 	if (vc4->gen >= VC4_GEN_6_C) {  in vc4_crtc_get_cob_allocation()
103 	return top - base + 4;  in vc4_crtc_get_cob_allocation()
112 	struct drm_device *dev = crtc->dev;  in vc4_crtc_get_scanout_position()
114 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_crtc_get_scanout_position()
116 	struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);  in vc4_crtc_get_scanout_position()
117 	unsigned int channel = vc4_crtc_state->assigned_channel;  in vc4_crtc_get_scanout_position()
134 	if (vc4->gen >= VC4_GEN_6_C)  in vc4_crtc_get_scanout_position()
147 	if (vc4->gen >= VC4_GEN_6_C)  in vc4_crtc_get_scanout_position()
154 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {  in vc4_crtc_get_scanout_position()
159 			*hpos += mode->crtc_htotal / 2;  in vc4_crtc_get_scanout_position()
163 	/* This is the offset we need for translating hvs -> pv scanout pos. */  in vc4_crtc_get_scanout_position()
164 	fifo_lines = cob_size / mode->crtc_hdisplay;  in vc4_crtc_get_scanout_position()
179 		 * incrementing vpos. Therefore we choose HVS read position -  in vc4_crtc_get_scanout_position()
183 		*vpos -= fifo_lines + 1;  in vc4_crtc_get_scanout_position()
191 	 * fifo with new lines from the top-most lines of the new framebuffers.  in vc4_crtc_get_scanout_position()
197 	vblank_lines = mode->vtotal - mode->vdisplay;  in vc4_crtc_get_scanout_position()
209 		*vpos = -vblank_lines;  in vc4_crtc_get_scanout_position()
212 			*stime = vc4_crtc->t_vblank;  in vc4_crtc_get_scanout_position()
214 			*etime = vc4_crtc->t_vblank;  in vc4_crtc_get_scanout_position()
242 	struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);  in vc4_get_fifo_full_level()
248 	u32 fifo_len_bytes = pv_data->fifo_depth;  in vc4_get_fifo_full_level()
263 		return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;  in vc4_get_fifo_full_level()
265 		return fifo_len_bytes - 14;  in vc4_get_fifo_full_level()
273 		if (crtc_data->hvs_output == 5)  in vc4_get_fifo_full_level()
289 		if (vc4->gen == VC4_GEN_4)  in vc4_get_fifo_full_level()
290 			return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;  in vc4_get_fifo_full_level()
292 		return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;  in vc4_get_fifo_full_level()
321 	WARN_ON(hweight32(state->encoder_mask) > 1);  in vc4_get_crtc_encoder()
323 	drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)  in vc4_get_crtc_encoder()
332 	struct drm_device *dev = crtc->dev;  in vc4_crtc_pixelvalve_reset()
348 	struct drm_device *dev = crtc->dev;  in vc4_crtc_config_pv()
353 	struct drm_crtc_state *crtc_state = crtc->state;  in vc4_crtc_config_pv()
354 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;  in vc4_crtc_config_pv()
355 	bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;  in vc4_crtc_config_pv()
356 	bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||  in vc4_crtc_config_pv()
357 		       vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;  in vc4_crtc_config_pv()
358 	u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;  in vc4_crtc_config_pv()
359 	bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||  in vc4_crtc_config_pv()
360 		       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);  in vc4_crtc_config_pv()
361 	bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;  in vc4_crtc_config_pv()
362 	bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;  in vc4_crtc_config_pv()
364 	u8 ppc = pv_data->pixels_per_clock;  in vc4_crtc_config_pv()
366 	u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;  in vc4_crtc_config_pv()
367 	u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;  in vc4_crtc_config_pv()
368 	u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;  in vc4_crtc_config_pv()
377 		struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);  in vc4_crtc_config_pv()
378 		dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",  in vc4_crtc_config_pv()
380 		drm_print_regset32(&p, &vc4_crtc->regset);  in vc4_crtc_config_pv()
386 		   VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,  in vc4_crtc_config_pv()
388 		   VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,  in vc4_crtc_config_pv()
392 		   VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,  in vc4_crtc_config_pv()
394 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,  in vc4_crtc_config_pv()
399 		u32 field_delay = mode->htotal * pixel_rep / (2 * ppc);  in vc4_crtc_config_pv()
406 			if (mode->htotal == 858) {  in vc4_crtc_config_pv()
407 				/* 525-line mode (NTSC or PAL-M) */  in vc4_crtc_config_pv()
422 			   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));  in vc4_crtc_config_pv()
424 		/* We set up first field even mode for HDMI and VEC's PAL.  in vc4_crtc_config_pv()
429 			   (vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |  in vc4_crtc_config_pv()
441 			   (vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |  in vc4_crtc_config_pv()
451 		   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));  in vc4_crtc_config_pv()
454 		CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);  in vc4_crtc_config_pv()
456 	if (vc4->gen >= VC4_GEN_5)  in vc4_crtc_config_pv()
461 	if (vc4->gen >= VC4_GEN_6_C)  in vc4_crtc_config_pv()
470 		   VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |  in vc4_crtc_config_pv()
474 		   VC4_SET_FIELD(vc4_encoder->clock_select,  in vc4_crtc_config_pv()
478 		struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);  in vc4_crtc_config_pv()
479 		dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",  in vc4_crtc_config_pv()
481 		drm_print_regset32(&p, &vc4_crtc->regset);  in vc4_crtc_config_pv()
490 	struct vc4_hvs *hvs = vc4->hvs;  in require_hvs_enabled()
492 	if (vc4->gen >= VC4_GEN_6_C)  in require_hvs_enabled()
505 	struct drm_device *dev = crtc->dev;  in vc4_crtc_disable()
510 		return -ENODEV;  in vc4_crtc_disable()
519 	 * unflushable FIFO between the pixelvalve and the HDMI  in vc4_crtc_disable()
535 	if (vc4_encoder && vc4_encoder->post_crtc_disable)  in vc4_crtc_disable()
536 		vc4_encoder->post_crtc_disable(encoder, state);  in vc4_crtc_disable()
539 	vc4_hvs_stop_channel(vc4->hvs, channel);  in vc4_crtc_disable()
541 	if (vc4_encoder && vc4_encoder->post_crtc_powerdown)  in vc4_crtc_disable()
542 		vc4_encoder->post_crtc_powerdown(encoder, state);  in vc4_crtc_disable()
551 	struct drm_device *drm = crtc->dev;  in vc4_crtc_disable_at_boot()
562 	if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,  in vc4_crtc_disable_at_boot()
563 				      "brcm,bcm2711-pixelvalve2") ||  in vc4_crtc_disable_at_boot()
564 	      of_device_is_compatible(vc4_crtc->pdev->dev.of_node,  in vc4_crtc_disable_at_boot()
565 				      "brcm,bcm2711-pixelvalve4") ||  in vc4_crtc_disable_at_boot()
566 	      of_device_is_compatible(vc4_crtc->pdev->dev.of_node,  in vc4_crtc_disable_at_boot()
567 				      "brcm,bcm2712-pixelvalve0") ||  in vc4_crtc_disable_at_boot()
568 	      of_device_is_compatible(vc4_crtc->pdev->dev.of_node,  in vc4_crtc_disable_at_boot()
569 				      "brcm,bcm2712-pixelvalve1")))  in vc4_crtc_disable_at_boot()
578 	channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);  in vc4_crtc_disable_at_boot()
587 	encoder_type = pv_data->encoder_types[encoder_sel];  in vc4_crtc_disable_at_boot()
593 	ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);  in vc4_crtc_disable_at_boot()
612 	struct drm_device *dev = crtc->dev;  in vc4_crtc_send_vblank()
615 	if (!crtc->state || !crtc->state->event)  in vc4_crtc_send_vblank()
618 	spin_lock_irqsave(&dev->event_lock, flags);  in vc4_crtc_send_vblank()
619 	drm_crtc_send_vblank_event(crtc, crtc->state->event);  in vc4_crtc_send_vblank()
620 	crtc->state->event = NULL;  in vc4_crtc_send_vblank()
621 	spin_unlock_irqrestore(&dev->event_lock, flags);  in vc4_crtc_send_vblank()
631 	struct drm_device *dev = crtc->dev;  in vc4_crtc_atomic_disable()
634 		crtc->name, crtc->base.id, encoder->name, encoder->base.id);  in vc4_crtc_atomic_disable()
641 	vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);  in vc4_crtc_atomic_disable()
655 	struct drm_device *dev = crtc->dev;  in vc4_crtc_atomic_enable()
662 		crtc->name, crtc->base.id, encoder->name, encoder->base.id);  in vc4_crtc_atomic_enable()
676 	if (vc4_encoder->pre_crtc_configure)  in vc4_crtc_atomic_enable()
677 		vc4_encoder->pre_crtc_configure(encoder, state);  in vc4_crtc_atomic_enable()
683 	if (vc4_encoder->pre_crtc_enable)  in vc4_crtc_atomic_enable()
684 		vc4_encoder->pre_crtc_enable(encoder, state);  in vc4_crtc_atomic_enable()
692 	if (vc4_encoder->post_crtc_enable)  in vc4_crtc_atomic_enable()
693 		vc4_encoder->post_crtc_enable(encoder, state);  in vc4_crtc_atomic_enable()
702 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {  in vc4_crtc_mode_valid()
704 			      crtc->base.id);  in vc4_crtc_mode_valid()
720 	*left = vc4_state->margins.left;  in vc4_crtc_get_margins()
721 	*right = vc4_state->margins.right;  in vc4_crtc_get_margins()
722 	*top = vc4_state->margins.top;  in vc4_crtc_get_margins()
723 	*bottom = vc4_state->margins.bottom;  in vc4_crtc_get_margins()
730 	for_each_new_connector_in_state(state->state, conn, conn_state, i) {  in vc4_crtc_get_margins()
731 		if (conn_state->crtc != state->crtc)  in vc4_crtc_get_margins()
734 		*left = conn_state->tv.margins.left;  in vc4_crtc_get_margins()
735 		*right = conn_state->tv.margins.right;  in vc4_crtc_get_margins()
736 		*top = conn_state->tv.margins.top;  in vc4_crtc_get_margins()
737 		*bottom = conn_state->tv.margins.bottom;  in vc4_crtc_get_margins()
759 		const struct drm_display_mode *mode = &crtc_state->adjusted_mode;  in vc4_crtc_atomic_check()
762 		if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {  in vc4_crtc_atomic_check()
763 			vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000,  in vc4_crtc_atomic_check()
764 						  mode->clock * 9 / 10) * 1000;  in vc4_crtc_atomic_check()
766 			vc4_state->hvs_load = mode->clock * 1000;  in vc4_crtc_atomic_check()
772 		if (conn_state->crtc != crtc)  in vc4_crtc_atomic_check()
775 		if (memcmp(&vc4_state->margins, &conn_state->tv.margins,  in vc4_crtc_atomic_check()
776 			   sizeof(vc4_state->margins))) {  in vc4_crtc_atomic_check()
777 			memcpy(&vc4_state->margins, &conn_state->tv.margins,  in vc4_crtc_atomic_check()
778 			       sizeof(vc4_state->margins));  in vc4_crtc_atomic_check()
784 			crtc_state->zpos_changed = true;  in vc4_crtc_atomic_check()
795 	struct drm_device *dev = crtc->dev;  in vc4_enable_vblank()
799 		return -ENODEV;  in vc4_enable_vblank()
811 	struct drm_device *dev = crtc->dev;  in vc4_disable_vblank()
824 	struct drm_crtc *crtc = &vc4_crtc->base;  in vc4_crtc_handle_page_flip()
825 	struct drm_device *dev = crtc->dev;  in vc4_crtc_handle_page_flip()
827 	struct vc4_hvs *hvs = vc4->hvs;  in vc4_crtc_handle_page_flip()
829 	u32 chan = vc4_crtc->current_hvs_channel;  in vc4_crtc_handle_page_flip()
832 	spin_lock_irqsave(&dev->event_lock, flags);  in vc4_crtc_handle_page_flip()
833 	spin_lock(&vc4_crtc->irq_lock);  in vc4_crtc_handle_page_flip()
835 	if (vc4->gen >= VC4_GEN_6_C)  in vc4_crtc_handle_page_flip()
841 	if (vc4_crtc->event &&  in vc4_crtc_handle_page_flip()
842 	    (vc4_crtc->current_dlist == current_dlist || vc4_crtc->feeds_txp)) {  in vc4_crtc_handle_page_flip()
843 		drm_crtc_send_vblank_event(crtc, vc4_crtc->event);  in vc4_crtc_handle_page_flip()
844 		vc4_crtc->event = NULL;  in vc4_crtc_handle_page_flip()
853 		if (vc4->gen < VC4_GEN_6_C)  in vc4_crtc_handle_page_flip()
856 	spin_unlock(&vc4_crtc->irq_lock);  in vc4_crtc_handle_page_flip()
857 	spin_unlock_irqrestore(&dev->event_lock, flags);  in vc4_crtc_handle_page_flip()
862 	crtc->t_vblank = ktime_get();  in vc4_crtc_handle_vblank()
863 	drm_crtc_handle_vblank(&crtc->base);  in vc4_crtc_handle_vblank()
900 	struct drm_crtc *crtc = flip_state->crtc;  in vc4_async_page_flip_complete()
901 	struct drm_device *dev = crtc->dev;  in vc4_async_page_flip_complete()
902 	struct drm_plane *plane = crtc->primary;  in vc4_async_page_flip_complete()
904 	vc4_plane_async_set_fb(plane, flip_state->fb);  in vc4_async_page_flip_complete()
905 	if (flip_state->event) {  in vc4_async_page_flip_complete()
908 		spin_lock_irqsave(&dev->event_lock, flags);  in vc4_async_page_flip_complete()
909 		drm_crtc_send_vblank_event(crtc, flip_state->event);  in vc4_async_page_flip_complete()
910 		spin_unlock_irqrestore(&dev->event_lock, flags);  in vc4_async_page_flip_complete()
914 	drm_framebuffer_put(flip_state->fb);  in vc4_async_page_flip_complete()
916 	if (flip_state->old_fb)  in vc4_async_page_flip_complete()
917 		drm_framebuffer_put(flip_state->old_fb);  in vc4_async_page_flip_complete()
928 	if (flip_state->old_fb) {  in vc4_async_page_flip_seqno_complete()
930 			drm_fb_dma_get_gem_obj(flip_state->old_fb, 0);  in vc4_async_page_flip_seqno_complete()
931 		bo = to_vc4_bo(&dma_bo->base);  in vc4_async_page_flip_seqno_complete()
941 	 * FIXME: we should move to generic async-page-flip when  in vc4_async_page_flip_seqno_complete()
943 	 * hand-made cleanup_fb() logic.  in vc4_async_page_flip_seqno_complete()
962 	struct drm_framebuffer *fb = flip_state->fb;  in vc4_async_set_fence_cb()
968 	if (vc4->gen == VC4_GEN_4) {  in vc4_async_set_fence_cb()
969 		struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);  in vc4_async_set_fence_cb()
971 		return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,  in vc4_async_set_fence_cb()
975 	ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);  in vc4_async_set_fence_cb()
981 		vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);  in vc4_async_set_fence_cb()
986 	if (dma_fence_add_callback(fence, &flip_state->cb.fence,  in vc4_async_set_fence_cb()
988 		vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);  in vc4_async_set_fence_cb()
999 	struct drm_device *dev = crtc->dev;  in vc4_async_page_flip_common()
1000 	struct drm_plane *plane = crtc->primary;  in vc4_async_page_flip_common()
1005 		return -ENOMEM;  in vc4_async_page_flip_common()
1008 	flip_state->fb = fb;  in vc4_async_page_flip_common()
1009 	flip_state->crtc = crtc;  in vc4_async_page_flip_common()
1010 	flip_state->event = event;  in vc4_async_page_flip_common()
1016 	 * FIXME: we should move to generic async-page-flip when it's  in vc4_async_page_flip_common()
1017 	 * available, so that we can get rid of this hand-made cleanup_fb()  in vc4_async_page_flip_common()
1020 	flip_state->old_fb = plane->state->fb;  in vc4_async_page_flip_common()
1021 	if (flip_state->old_fb)  in vc4_async_page_flip_common()
1022 		drm_framebuffer_get(flip_state->old_fb);  in vc4_async_page_flip_common()
1030 	drm_atomic_set_fb_for_plane(plane->state, fb);  in vc4_async_page_flip_common()
1038 /* Implements async (non-vblank-synced) page flips.
1049 	struct drm_device *dev = crtc->dev;  in vc4_async_page_flip()
1052 	struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);  in vc4_async_page_flip()
1055 	if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))  in vc4_async_page_flip()
1056 		return -ENODEV;  in vc4_async_page_flip()
1061 	 * plane is later updated through the non-async path.  in vc4_async_page_flip()
1063 	 * FIXME: we should move to generic async-page-flip when  in vc4_async_page_flip()
1065 	 * hand-made prepare_fb() logic.  in vc4_async_page_flip()
1095 		struct drm_device *dev = crtc->dev;  in vc4_page_flip()
1098 		if (vc4->gen > VC4_GEN_4)  in vc4_page_flip()
1115 	old_vc4_state = to_vc4_crtc_state(crtc->state);  in vc4_crtc_duplicate_state()
1116 	vc4_state->margins = old_vc4_state->margins;  in vc4_crtc_duplicate_state()
1117 	vc4_state->assigned_channel = old_vc4_state->assigned_channel;  in vc4_crtc_duplicate_state()
1119 	__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);  in vc4_crtc_duplicate_state()
1120 	return &vc4_state->base;  in vc4_crtc_duplicate_state()
1126 	struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);  in vc4_crtc_destroy_state()
1129 	if (drm_mm_node_allocated(&vc4_state->mm)) {  in vc4_crtc_destroy_state()
1132 		spin_lock_irqsave(&vc4->hvs->mm_lock, flags);  in vc4_crtc_destroy_state()
1133 		drm_mm_remove_node(&vc4_state->mm);  in vc4_crtc_destroy_state()
1134 		spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);  in vc4_crtc_destroy_state()
1145 	if (crtc->state)  in vc4_crtc_reset()
1146 		vc4_crtc_destroy_state(crtc, crtc->state);  in vc4_crtc_reset()
1150 		crtc->state = NULL;  in vc4_crtc_reset()
1154 	vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;  in vc4_crtc_reset()
1155 	__drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);  in vc4_crtc_reset()
1160 	struct drm_device *drm = crtc->dev;  in vc4_crtc_late_register()
1164 	vc4_debugfs_add_regset32(drm, crtc_data->debugfs_name,  in vc4_crtc_late_register()
1165 				 &vc4_crtc->regset);  in vc4_crtc_late_register()
1197 		.name = "pixelvalve-0",
1212 		.name = "pixelvalve-1",
1227 		.name = "pixelvalve-2",
1242 		.name = "pixelvalve-0",
1257 		.name = "pixelvalve-1",
1272 		.name = "pixelvalve-2",
1286 		.name = "pixelvalve-3",
1300 		.name = "pixelvalve-4",
1339 	{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1340 	{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1341 	{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1342 	{ .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1343 	{ .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1344 	{ .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1345 	{ .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1346 	{ .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1347 	{ .compatible = "brcm,bcm2712-pixelvalve0", .data = &bcm2712_pv0_data },
1348 	{ .compatible = "brcm,bcm2712-pixelvalve1", .data = &bcm2712_pv1_data },
1357 	const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;  in vc4_set_crtc_possible_masks()
1364 		if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)  in vc4_set_crtc_possible_masks()
1368 		for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {  in vc4_set_crtc_possible_masks()
1369 			if (vc4_encoder->type == encoder_types[i]) {  in vc4_set_crtc_possible_masks()
1370 				vc4_encoder->clock_select = i;  in vc4_set_crtc_possible_masks()
1371 				encoder->possible_crtcs |= drm_crtc_mask(crtc);  in vc4_set_crtc_possible_masks()
1379  * __vc4_crtc_init - Initializes a CRTC
1406 	struct drm_crtc *crtc = &vc4_crtc->base;  in __vc4_crtc_init()
1410 	vc4_crtc->data = data;  in __vc4_crtc_init()
1411 	vc4_crtc->pdev = pdev;  in __vc4_crtc_init()
1412 	vc4_crtc->feeds_txp = feeds_txp;  in __vc4_crtc_init()
1413 	spin_lock_init(&vc4_crtc->irq_lock);  in __vc4_crtc_init()
1415 					 crtc_funcs, data->name);  in __vc4_crtc_init()
1421 	if (vc4->gen == VC4_GEN_4) {  in __vc4_crtc_init()
1422 		drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));  in __vc4_crtc_init()
1423 		drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);  in __vc4_crtc_init()
1428 		drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);  in __vc4_crtc_init()
1431 	for (i = 0; i < crtc->gamma_size; i++) {  in __vc4_crtc_init()
1432 		vc4_crtc->lut_r[i] = i;  in __vc4_crtc_init()
1433 		vc4_crtc->lut_g[i] = i;  in __vc4_crtc_init()
1434 		vc4_crtc->lut_b[i] = i;  in __vc4_crtc_init()
1457 		dev_err(drm->dev, "failed to construct primary plane\n");  in vc4_crtc_init()
1476 		return -ENOMEM;  in vc4_crtc_bind()
1477 	crtc = &vc4_crtc->base;  in vc4_crtc_bind()
1481 		return -ENODEV;  in vc4_crtc_bind()
1483 	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);  in vc4_crtc_bind()
1484 	if (IS_ERR(vc4_crtc->regs))  in vc4_crtc_bind()
1485 		return PTR_ERR(vc4_crtc->regs);  in vc4_crtc_bind()
1487 	vc4_crtc->regset.base = vc4_crtc->regs;  in vc4_crtc_bind()
1488 	vc4_crtc->regset.regs = crtc_regs;  in vc4_crtc_bind()
1489 	vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);  in vc4_crtc_bind()
1491 	ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base,  in vc4_crtc_bind()
1530 	return component_add(&pdev->dev, &vc4_crtc_ops);  in vc4_crtc_dev_probe()
1535 	component_del(&pdev->dev, &vc4_crtc_ops);  in vc4_crtc_dev_remove()