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1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8
60 # define V3D_V7_HUB_INT_GMPV BIT(6)
61 # define V3D_HUB_INT_MMU_WRV BIT(5)
62 # define V3D_HUB_INT_MMU_PTI BIT(4)
63 # define V3D_HUB_INT_MMU_CAP BIT(3)
64 # define V3D_HUB_INT_MSO BIT(2)
65 # define V3D_HUB_INT_TFUC BIT(1)
66 # define V3D_HUB_INT_TFUF BIT(0)
70 # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0)
73 # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0)
79 # define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8)
80 # define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8
86 # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0)
89 # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
94 # define V3D_TFU_CS_TFURST BIT(31)
97 # define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8)
98 # define V3D_TFU_CS_NFREE_SHIFT 8
99 # define V3D_TFU_CS_BUSY BIT(0)
103 # define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8)
104 # define V3D_TFU_SU_FINTTHR_SHIFT 8
106 # define V3D_TFU_SU_CRCCHAIN BIT(4)
108 # define V3D_TFU_SU_CRC BIT(3)
114 # define V3D_TFU_ICFG_IOC BIT(0)
122 /* Input Image U-Plane Address */
133 # define V3D_TFU_COEF0_USECOEF BIT(31)
144 /* Per-MMU registers. */
147 #define V3D_MMUC_CONTROL_CLEAR(ver) ((ver >= 71) ? BIT(11) : BIT(3))
148 # define V3D_MMUC_CONTROL_FLUSHING BIT(2)
149 # define V3D_MMUC_CONTROL_FLUSH BIT(1)
150 # define V3D_MMUC_CONTROL_ENABLE BIT(0)
153 # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27)
154 # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26)
155 # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25)
156 # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24)
157 # define V3D_MMU_CTL_PT_INVALID BIT(20)
158 # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19)
159 # define V3D_MMU_CTL_PT_INVALID_INT BIT(18)
160 # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17)
161 # define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16)
162 # define V3D_MMU_CTL_WRITE_VIOLATION BIT(12)
163 # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11)
164 # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10)
165 # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9)
166 # define V3D_MMU_CTL_TLB_CLEARING BIT(7)
167 # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3)
168 # define V3D_MMU_CTL_TLB_CLEAR BIT(2)
169 # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1)
170 # define V3D_MMU_CTL_ENABLE BIT(0)
178 # define V3D_MMU_ADDR_CAP_ENABLE BIT(31)
183 # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29)
184 # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28)
196 # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31)
202 # define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
203 # define V3D_MMU_PA_WIDTH_SHIFT 8
209 /* Per-V3D-core registers */
223 # define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8)
224 # define V3D_IDENT1_QUPS_SHIFT 8
231 # define V3D_IDENT2_BCG_INT BIT(28)
236 # define V3D_MISCCFG_OVRTMUOUT BIT(0)
239 # define V3D_L2CACTL_L2CCLR BIT(2)
240 # define V3D_L2CACTL_L2CDIS BIT(1)
241 # define V3D_L2CACTL_L2CENA BIT(0)
248 # define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8)
249 # define V3D_SLCACTL_UCC_SHIFT 8
254 # define V3D_L2TCACTL_TMUWCF BIT(8)
263 # define V3D_L2TCACTL_L2TFLS BIT(0)
275 #define V3D_INT_CSDDONE(ver) ((ver >= 71) ? BIT(6) : BIT(7))
276 #define V3D_INT_PCTR(ver) ((ver >= 71) ? BIT(5) : BIT(6))
277 # define V3D_INT_GMPV BIT(5)
278 # define V3D_INT_TRFB BIT(4)
279 # define V3D_INT_SPILLUSE BIT(3)
280 # define V3D_INT_OUTOMEM BIT(2)
281 # define V3D_INT_FLDONE BIT(1)
282 # define V3D_INT_FRDONE BIT(0)
312 # define V3D_CLE_CT0QTS_ENABLE BIT(1)
323 # define V3D_CLE_QCFG_ETFILT BIT(7)
327 # define V3D_CLE_QCFG_ETPROC BIT(6)
328 # define V3D_CLE_QCFG_ETSFLUSH BIT(1)
329 # define V3D_CLE_QCFG_MCDIS BIT(0)
337 # define V3D_PTB_BXCF_RWORDERDISA BIT(1)
338 # define V3D_PTB_BXCF_CLIPDISA BIT(0)
341 #define V3D_V3_PCTR_0_EN_ENABLE BIT(31)
343 /* When a bit is set, resets the counter to 0. */
360 # define V3D_PCTR_S1_MASK V3D_MASK(14, 8)
361 # define V3D_V7_PCTR_S1_MASK V3D_MASK(15, 8)
362 # define V3D_PCTR_S1_SHIFT 8
377 # define V3D_GMP_STATUS_GMPRST BIT(31)
382 # define V3D_GMP_STATUS_WR_ACTIVE BIT(5)
383 # define V3D_GMP_STATUS_RD_ACTIVE BIT(4)
384 # define V3D_GMP_STATUS_CFG_BUSY BIT(3)
385 # define V3D_GMP_STATUS_CNTOVF BIT(2)
386 # define V3D_GMP_STATUS_INVPROT BIT(1)
387 # define V3D_GMP_STATUS_VIO BIT(0)
390 # define V3D_GMP_CFG_LBURSTEN BIT(3)
391 # define V3D_GMP_CFG_PGCRSEN BIT()
392 # define V3D_GMP_CFG_STOP_REQ BIT(1)
393 # define V3D_GMP_CFG_PROT_ENABLE BIT(0)
407 # define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1)
408 # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
429 # define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26)
434 # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8)
435 # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8
464 # define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8)
465 # define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8
480 # define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17)
481 # define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16)
482 # define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14)
483 # define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13)
484 # define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12)
485 # define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11)
486 # define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7)
487 # define V3D_ERR_FDBGS_EZTEST_PASS BIT(6)
488 # define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5)
489 # define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4)
490 # define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3)
491 # define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2)
492 # define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1)
493 # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
496 # define V3D_ERR_L2CARE BIT(15)
497 # define V3D_ERR_VCMBE BIT(14)
498 # define V3D_ERR_VCMRE BIT(13)
499 # define V3D_ERR_VCDI BIT(12)
500 # define V3D_ERR_VCDE BIT(11)
501 # define V3D_ERR_VDWE BIT(10)
502 # define V3D_ERR_VPMEAS BIT(9)
503 # define V3D_ERR_VPMEFNA BIT(8)
504 # define V3D_ERR_VPMEWNA BIT(7)
505 # define V3D_ERR_VPMERNA BIT(6)
506 # define V3D_ERR_VPMERR BIT(5)
507 # define V3D_ERR_VPMEWR BIT(4)
508 # define V3D_ERR_VPAERRGL BIT(3)
509 # define V3D_ERR_VPAEBRGL BIT(2)
510 # define V3D_ERR_VPAERGS BIT(1)
511 # define V3D_ERR_VPAEABB BIT(0)