1 // SPDX-License-Identifier: GPL-2.0
13 …{"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rende…
14 …{"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (pr…
15 	{"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"},
16 	{"FEP", "FEP-valid-quads", "[FEP] Valid quads"},
17 …{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test…
18 …{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and …
19 …{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and ste…
20 	{"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"},
21 …{"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"…
22 …{"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buff…
23 …{"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside …
24 	{"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"},
25 …{"PTB", "PTB-primitives-discarded-reversed", "[PTB] Primitives that are discarded because they are…
26 	{"QPU", "QPU-total-idle-clk-cycles", "[QPU] Total idle clock cycles for all QPUs"},
27 …{"QPU", "QPU-total-active-clk-cycles-vertex-coord-shading", "[QPU] Total active clock cycles for a…
28 …{"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all Q…
29 …{"QPU", "QPU-total-clk-cycles-executing-valid-instr", "[QPU] Total clock cycles for all QPUs execu…
30 …{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting…
31 …{"QPU", "QPU-total-clk-cycles-waiting-scoreboard", "[QPU] Total clock cycles for all QPUs stalled …
32 …{"QPU", "QPU-total-clk-cycles-waiting-varyings", "[QPU] Total clock cycles for all QPUs stalled wa…
33 	{"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
34 	{"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
35 	{"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
36 	{"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
37 	{"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
39 …{"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for V…
40 …{"VPM", "VPM-total-clk-cycles-VCD-stalled", "[VPM] Total clock cycles VCD is stalled waiting for V…
41 	{"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"},
42 	{"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"},
43 	{"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"},
44 	{"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"},
45 	{"CORE", "cycle-count", "[CORE] Cycle counter"},
46 …{"QPU", "QPU-total-clk-cycles-waiting-vertex-coord-shading", "[QPU] Total stalled clock cycles for…
47 …{"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all…
48 	{"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"},
49 	{"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"},
50 	{"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"},
51 	{"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"},
52 	{"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"},
53 	{"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"},
54 	{"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
55 	{"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"},
56 	{"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"},
57 	{"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"},
58 	{"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"},
59 	{"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"},
60 	{"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
61 …{"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour bu…
62 	{"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
63 	{"L2T", "L2T-no-id-stalled", "[L2T] No ID stall"},
64 	{"L2T", "L2T-command-queue-stalled", "[L2T] Command queue full stall"},
65 	{"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
66 	{"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
67 	{"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
68 	{"CLE", "CLE-thread-active-cycles", "[CLE] Bin or render thread active cycles"},
69 	{"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
70 	{"L2T", "L2T-CLE-reads", "[L2T] CLE read accesses"},
71 	{"L2T", "L2T-VCD-reads", "[L2T] VCD read accesses"},
72 	{"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
73 	{"L2T", "L2T-SLC0-reads", "[L2T] SLC0 read accesses"},
74 	{"L2T", "L2T-SLC1-reads", "[L2T] SLC1 read accesses"},
75 	{"L2T", "L2T-SLC2-reads", "[L2T] SLC2 read accesses"},
76 	{"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"},
77 	{"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
78 	{"L2T", "L2T-CLE-read-miss", "[L2T] CLE read misses"},
79 	{"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"},
80 	{"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"},
81 	{"L2T", "L2T-SLC0-read-miss", "[L2T] SLC0 read misses"},
82 	{"L2T", "L2T-SLC1-read-miss", "[L2T] SLC1 read misses"},
83 	{"L2T", "L2T-SLC2-read-miss", "[L2T] SLC2 read misses"},
84 	{"CORE", "core-memory-writes", "[CORE] Total memory writes"},
85 	{"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
86 	{"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
87 	{"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
88 	{"CORE", "core-memory-reads", "[CORE] Total memory reads"},
89 	{"L2T", "L2T-memory-reads", "[L2T] Total memory reads"},
90 	{"PTB", "PTB-memory-reads", "[PTB] Total memory reads"},
91 	{"PSE", "PSE-memory-reads", "[PSE] Total memory reads"},
92 	{"TLB", "TLB-memory-reads", "[TLB] Total memory reads"},
93 	{"GMP", "GMP-memory-reads", "[GMP] Total memory reads"},
94 	{"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
95 	{"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
96 	{"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
97 	{"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
98 	{"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"},
99 	{"CORE", "compute-active-cycles", "[CORE] Compute active cycles"},
103 	{"CORE", "cycle-count", "[CORE] Cycle counter"},
104 	{"CORE", "core-active", "[CORE] Bin/Render/Compute active cycles"},
105 	{"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"},
106 	{"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"},
107 	{"CORE", "compute-active-cycles", "[CORE] Compute active cycles"},
108 …{"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rende…
109 …{"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (pr…
110 	{"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"},
111 	{"FEP", "FEP-valid-quads", "[FEP] Valid quads"},
112 …{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test…
113 …{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and …
114 …{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and ste…
115 …{"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buff…
116 …{"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour bu…
117 	{"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"},
118 …{"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside …
119 	{"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"},
120 …{"PTB", "PTB-primitives-discarded-reversed", "[PTB] Primitives that are discarded because they are…
121 	{"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
122 	{"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
123 	{"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
124 	{"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
125 	{"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
126 	{"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
127 	{"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
128 	{"TMU", "TMU-cache-x4-active-cycles", "[TMU] Cache active cycles for x4 access"},
129 	{"TMU", "TMU-cache-x4-stalled-cycles", "[TMU] Cache stalled cycles for x4 access"},
130 	{"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"},
131 	{"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"},
132 	{"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"},
133 	{"L2T", "L2T-local", "[L2T] Local mode access"},
134 	{"L2T", "L2T-writeback", "[L2T] Writeback"},
135 	{"L2T", "L2T-zero", "[L2T] Zero"},
136 	{"L2T", "L2T-merge", "[L2T] Merge"},
137 	{"L2T", "L2T-fill", "[L2T] Fill"},
138 	{"L2T", "L2T-stalls-no-wid", "[L2T] Stalls because no WID available"},
139 	{"L2T", "L2T-stalls-no-rid", "[L2T] Stalls because no RID available"},
140 	{"L2T", "L2T-stalls-queue-full", "[L2T] Stalls because internal queue full"},
141 	{"L2T", "L2T-stalls-wrightback", "[L2T] Stalls because writeback in flight"},
142 	{"L2T", "L2T-stalls-mem", "[L2T] Stalls because AXI blocks read"},
143 	{"L2T", "L2T-stalls-fill", "[L2T] Stalls because fill pending for victim cache-line"},
144 	{"L2T", "L2T-hitq", "[L2T] Sent request via hit queue"},
145 	{"L2T", "L2T-hitq-full", "[L2T] Sent request via main queue because hit queue is full"},
146 	{"L2T", "L2T-stalls-read-data", "[L2T] Stalls because waiting for data from SDRAM"},
147 	{"L2T", "L2T-TMU-read-hits", "[L2T] TMU read hits"},
148 	{"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
149 	{"L2T", "L2T-VCD-read-hits", "[L2T] VCD read hits"},
150 	{"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"},
151 	{"L2T", "L2T-SLC-read-hits", "[L2T] SLC read hits (all slices)"},
152 	{"L2T", "L2T-SLC-read-miss", "[L2T] SLC read misses (all slices)"},
153 	{"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"},
154 	{"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"},
155 	{"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"},
156 	{"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"},
157 	{"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"},
158 	{"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
159 	{"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"},
160 	{"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"},
161 	{"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"},
162 	{"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"},
163 	{"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"},
164 	{"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
165 	{"CORE", "core-memory-writes", "[CORE] Total memory writes"},
166 	{"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
167 	{"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
168 	{"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
169 	{"CORE", "core-memory-reads", "[CORE] Total memory reads"},
170 	{"L2T", "L2T-memory-reads", "[L2T] Total memory reads"},
171 	{"PTB", "PTB-memory-reads", "[PTB] Total memory reads"},
172 	{"PSE", "PSE-memory-reads", "[PSE] Total memory reads"},
173 	{"TLB", "TLB-memory-reads", "[TLB] Total memory reads"},
174 	{"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
175 	{"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
176 	{"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
177 	{"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
178 	{"AXI", "AXI-read-trans", "[AXI] Read transaction count"},
179 	{"AXI", "AXI-write-trans", "[AXI] Write transaction count"},
180 	{"AXI", "AXI-read-wait-cycles", "[AXI] Read total wait cycles"},
181 	{"AXI", "AXI-write-wait-cycles", "[AXI] Write total wait cycles"},
182 	{"AXI", "AXI-max-outstanding-reads", "[AXI] Maximum outstanding read transactions"},
183 	{"AXI", "AXI-max-outstanding-writes", "[AXI] Maximum outstanding write transactions"},
184 	{"QPU", "QPU-wait-bubble", "[QPU] Pipeline bubble in qcycles due all threads waiting"},
185 	{"QPU", "QPU-ic-miss-bubble", "[QPU] Pipeline bubble in qcycles due instruction-cache miss"},
186 	{"QPU", "QPU-active", "[QPU] Executed shader instruction"},
187 …{"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all Q…
188 	{"QPU", "QPU-stalls", "[QPU] Stalled qcycles executing shader instruction"},
189 …{"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all…
190 	{"QPU", "QPU-stalls-TMU", "[QPU] Stalled qcycles waiting for TMU"},
191 	{"QPU", "QPU-stalls-TLB", "[QPU] Stalled qcycles waiting for TLB"},
192 	{"QPU", "QPU-stalls-VPM", "[QPU] Stalled qcycles waiting for VPM"},
193 	{"QPU", "QPU-stalls-uniforms", "[QPU] Stalled qcycles waiting for uniforms"},
194 	{"QPU", "QPU-stalls-SFU", "[QPU] Stalled qcycles waiting for SFU"},
195 	{"QPU", "QPU-stalls-other", "[QPU] Stalled qcycles waiting for any other reason (vary/W/Z)"},
203 	if (v3d->ver >= 71) {  in v3d_perfmon_init()
206 	} else if (v3d->ver >= 42) {  in v3d_perfmon_init()
211 	v3d->perfmon_info.max_counters = max;  in v3d_perfmon_init()
212 	v3d->perfmon_info.counters = counters;  in v3d_perfmon_init()
218 		refcount_inc(&perfmon->refcnt);  in v3d_perfmon_get()
223 	if (perfmon && refcount_dec_and_test(&perfmon->refcnt)) {  in v3d_perfmon_put()
224 		mutex_destroy(&perfmon->lock);  in v3d_perfmon_put()
235 	if (WARN_ON_ONCE(!perfmon || v3d->active_perfmon))  in v3d_perfmon_start()
238 	ncounters = perfmon->ncounters;  in v3d_perfmon_start()
239 	mask = GENMASK(ncounters - 1, 0);  in v3d_perfmon_start()
243 		u32 channel = V3D_SET_FIELD(perfmon->counters[i], V3D_PCTR_S0);  in v3d_perfmon_start()
246 		channel |= V3D_SET_FIELD(i < ncounters ? perfmon->counters[i] : 0,  in v3d_perfmon_start()
249 		channel |= V3D_SET_FIELD(i < ncounters ? perfmon->counters[i] : 0,  in v3d_perfmon_start()
252 		channel |= V3D_SET_FIELD(i < ncounters ? perfmon->counters[i] : 0,  in v3d_perfmon_start()
261 	v3d->active_perfmon = perfmon;  in v3d_perfmon_start()
269 	if (!perfmon || !v3d->active_perfmon)  in v3d_perfmon_stop()
272 	mutex_lock(&perfmon->lock);  in v3d_perfmon_stop()
273 	if (perfmon != v3d->active_perfmon) {  in v3d_perfmon_stop()
274 		mutex_unlock(&perfmon->lock);  in v3d_perfmon_stop()
279 		for (i = 0; i < perfmon->ncounters; i++)  in v3d_perfmon_stop()
280 			perfmon->values[i] += V3D_CORE_READ(0, V3D_PCTR_0_PCTRX(i));  in v3d_perfmon_stop()
284 	v3d->active_perfmon = NULL;  in v3d_perfmon_stop()
285 	mutex_unlock(&perfmon->lock);  in v3d_perfmon_stop()
292 	mutex_lock(&v3d_priv->perfmon.lock);  in v3d_perfmon_find()
293 	perfmon = idr_find(&v3d_priv->perfmon.idr, id);  in v3d_perfmon_find()
295 	mutex_unlock(&v3d_priv->perfmon.lock);  in v3d_perfmon_find()
302 	mutex_init(&v3d_priv->perfmon.lock);  in v3d_perfmon_open_file()
303 	idr_init_base(&v3d_priv->perfmon.idr, 1);  in v3d_perfmon_open_file()
312 	if (perfmon == v3d->active_perfmon)  in v3d_perfmon_idr_del()
322 	struct v3d_dev *v3d = v3d_priv->v3d;  in v3d_perfmon_close_file()
324 	mutex_lock(&v3d_priv->perfmon.lock);  in v3d_perfmon_close_file()
325 	idr_for_each(&v3d_priv->perfmon.idr, v3d_perfmon_idr_del, v3d);  in v3d_perfmon_close_file()
326 	idr_destroy(&v3d_priv->perfmon.idr);  in v3d_perfmon_close_file()
327 	mutex_unlock(&v3d_priv->perfmon.lock);  in v3d_perfmon_close_file()
328 	mutex_destroy(&v3d_priv->perfmon.lock);  in v3d_perfmon_close_file()
334 	struct v3d_file_priv *v3d_priv = file_priv->driver_priv;  in v3d_perfmon_create_ioctl()
336 	struct v3d_dev *v3d = v3d_priv->v3d;  in v3d_perfmon_create_ioctl()
342 	if (req->ncounters > DRM_V3D_MAX_PERF_COUNTERS ||  in v3d_perfmon_create_ioctl()
343 	    !req->ncounters)  in v3d_perfmon_create_ioctl()
344 		return -EINVAL;  in v3d_perfmon_create_ioctl()
347 	for (i = 0; i < req->ncounters; i++) {  in v3d_perfmon_create_ioctl()
348 		if (req->counters[i] >= v3d->perfmon_info.max_counters)  in v3d_perfmon_create_ioctl()
349 			return -EINVAL;  in v3d_perfmon_create_ioctl()
352 	perfmon = kzalloc(struct_size(perfmon, values, req->ncounters),  in v3d_perfmon_create_ioctl()
355 		return -ENOMEM;  in v3d_perfmon_create_ioctl()
357 	for (i = 0; i < req->ncounters; i++)  in v3d_perfmon_create_ioctl()
358 		perfmon->counters[i] = req->counters[i];  in v3d_perfmon_create_ioctl()
360 	perfmon->ncounters = req->ncounters;  in v3d_perfmon_create_ioctl()
362 	refcount_set(&perfmon->refcnt, 1);  in v3d_perfmon_create_ioctl()
363 	mutex_init(&perfmon->lock);  in v3d_perfmon_create_ioctl()
365 	mutex_lock(&v3d_priv->perfmon.lock);  in v3d_perfmon_create_ioctl()
366 	ret = idr_alloc(&v3d_priv->perfmon.idr, perfmon, V3D_PERFMONID_MIN,  in v3d_perfmon_create_ioctl()
368 	mutex_unlock(&v3d_priv->perfmon.lock);  in v3d_perfmon_create_ioctl()
371 		mutex_destroy(&perfmon->lock);  in v3d_perfmon_create_ioctl()
376 	req->id = ret;  in v3d_perfmon_create_ioctl()
384 	struct v3d_file_priv *v3d_priv = file_priv->driver_priv;  in v3d_perfmon_destroy_ioctl()
388 	mutex_lock(&v3d_priv->perfmon.lock);  in v3d_perfmon_destroy_ioctl()
389 	perfmon = idr_remove(&v3d_priv->perfmon.idr, req->id);  in v3d_perfmon_destroy_ioctl()
390 	mutex_unlock(&v3d_priv->perfmon.lock);  in v3d_perfmon_destroy_ioctl()
393 		return -EINVAL;  in v3d_perfmon_destroy_ioctl()
404 	struct v3d_file_priv *v3d_priv = file_priv->driver_priv;  in v3d_perfmon_get_values_ioctl()
409 	if (req->pad != 0)  in v3d_perfmon_get_values_ioctl()
410 		return -EINVAL;  in v3d_perfmon_get_values_ioctl()
412 	mutex_lock(&v3d_priv->perfmon.lock);  in v3d_perfmon_get_values_ioctl()
413 	perfmon = idr_find(&v3d_priv->perfmon.idr, req->id);  in v3d_perfmon_get_values_ioctl()
415 	mutex_unlock(&v3d_priv->perfmon.lock);  in v3d_perfmon_get_values_ioctl()
418 		return -EINVAL;  in v3d_perfmon_get_values_ioctl()
422 	if (copy_to_user(u64_to_user_ptr(req->values_ptr), perfmon->values,  in v3d_perfmon_get_values_ioctl()
423 			 perfmon->ncounters * sizeof(u64)))  in v3d_perfmon_get_values_ioctl()
424 		ret = -EFAULT;  in v3d_perfmon_get_values_ioctl()
438 	for (int i = 0; i < ARRAY_SIZE(req->reserved); i++) {  in v3d_perfmon_get_counter_ioctl()
439 		if (req->reserved[i] != 0)  in v3d_perfmon_get_counter_ioctl()
440 			return -EINVAL;  in v3d_perfmon_get_counter_ioctl()
443 	if (!v3d->perfmon_info.max_counters)  in v3d_perfmon_get_counter_ioctl()
444 		return -EOPNOTSUPP;  in v3d_perfmon_get_counter_ioctl()
447 	if (req->counter >= v3d->perfmon_info.max_counters)  in v3d_perfmon_get_counter_ioctl()
448 		return -EINVAL;  in v3d_perfmon_get_counter_ioctl()
450 	counter = &v3d->perfmon_info.counters[req->counter];  in v3d_perfmon_get_counter_ioctl()
452 	strscpy(req->name, counter->name, sizeof(req->name));  in v3d_perfmon_get_counter_ioctl()
453 	strscpy(req->category, counter->category, sizeof(req->category));  in v3d_perfmon_get_counter_ioctl()
454 	strscpy(req->description, counter->description, sizeof(req->description));  in v3d_perfmon_get_counter_ioctl()