Lines Matching full:read
52 {"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"},
54 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
58 {"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"},
60 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
69 {"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
70 {"L2T", "L2T-CLE-reads", "[L2T] CLE read accesses"},
71 {"L2T", "L2T-VCD-reads", "[L2T] VCD read accesses"},
72 {"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
73 {"L2T", "L2T-SLC0-reads", "[L2T] SLC0 read accesses"},
74 {"L2T", "L2T-SLC1-reads", "[L2T] SLC1 read accesses"},
75 {"L2T", "L2T-SLC2-reads", "[L2T] SLC2 read accesses"},
77 {"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
78 {"L2T", "L2T-CLE-read-miss", "[L2T] CLE read misses"},
79 {"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"},
80 {"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"},
81 {"L2T", "L2T-SLC0-read-miss", "[L2T] SLC0 read misses"},
82 {"L2T", "L2T-SLC1-read-miss", "[L2T] SLC1 read misses"},
83 {"L2T", "L2T-SLC2-read-miss", "[L2T] SLC2 read misses"},
96 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
97 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
142 {"L2T", "L2T-stalls-mem", "[L2T] Stalls because AXI blocks read"},
146 {"L2T", "L2T-stalls-read-data", "[L2T] Stalls because waiting for data from SDRAM"},
147 {"L2T", "L2T-TMU-read-hits", "[L2T] TMU read hits"},
148 {"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
149 {"L2T", "L2T-VCD-read-hits", "[L2T] VCD read hits"},
150 {"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"},
151 {"L2T", "L2T-SLC-read-hits", "[L2T] SLC read hits (all slices)"},
152 {"L2T", "L2T-SLC-read-miss", "[L2T] SLC read misses (all slices)"},
156 {"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"},
158 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
162 {"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"},
164 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
176 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
177 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
178 {"AXI", "AXI-read-trans", "[AXI] Read transaction count"},
180 {"AXI", "AXI-read-wait-cycles", "[AXI] Read total wait cycles"},
182 {"AXI", "AXI-max-outstanding-reads", "[AXI] Maximum outstanding read transactions"},