195 v3d_has_csd(struct v3d_dev *v3d)  in v3d_has_csd()  argument
197 	return v3d->ver >= 41;  in v3d_has_csd()
200 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)  argument
204 	struct v3d_dev *v3d;  member
250 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
251 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
253 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
254 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
256 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
257 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
259 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
260 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
267 	struct v3d_dev *v3d;  member
532 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
537 void v3d_reset(struct v3d_dev *v3d);
538 void v3d_invalidate_caches(struct v3d_dev *v3d);
539 void v3d_clean_caches(struct v3d_dev *v3d);
543 void v3d_gemfs_init(struct v3d_dev *v3d);
544 void v3d_gemfs_fini(struct v3d_dev *v3d);
559 int v3d_irq_init(struct v3d_dev *v3d);
560 void v3d_irq_enable(struct v3d_dev *v3d);
561 void v3d_irq_disable(struct v3d_dev *v3d);
562 void v3d_irq_reset(struct v3d_dev *v3d);
565 int v3d_mmu_flush_all(struct v3d_dev *v3d);
566 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
576 int v3d_sched_init(struct v3d_dev *v3d);
577 void v3d_sched_fini(struct v3d_dev *v3d);
580 void v3d_perfmon_init(struct v3d_dev *v3d);
583 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
584 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,