Lines Matching refs:dispc_vid_write
525 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
638 dispc_vid_write(dispc, hw_plane, idx,
752 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);
784 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);
1483 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,
1648 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1667 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1819 dispc_vid_write(dispc, hw_plane, reg, c0);
1831 dispc_vid_write(dispc, hw_plane, reg, c12);
2043 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
2050 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,
2059 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);
2066 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);
2245 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
2246 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
2247 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
2248 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
2250 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
2255 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2258 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2261 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
2271 dispc_vid_write(dispc, hw_plane,
2273 dispc_vid_write(dispc, hw_plane,
2275 dispc_vid_write(dispc, hw_plane,
2277 dispc_vid_write(dispc, hw_plane,
2280 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,
2287 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,
2302 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
2326 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,
2333 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,
2375 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2430 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);