Lines Matching defs:hw_videoport
539 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
542 void __iomem *base = dispc->base_ovr[hw_videoport];
547 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
549 void __iomem *base = dispc->base_ovr[hw_videoport];
554 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
557 void __iomem *base = dispc->base_vp[hw_videoport];
562 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
564 void __iomem *base = dispc->base_vp[hw_videoport];
569 int tidss_configure_oldi(struct tidss_device *tidss, u32 hw_videoport,
573 u32 oldi_reset_bit = BIT(5 + hw_videoport);
575 dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
587 void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
589 dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
671 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport)
676 vp_stat |= DSS_IRQ_VP_FRAME_DONE(hw_videoport);
678 vp_stat |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport);
680 vp_stat |= DSS_IRQ_VP_VSYNC_ODD(hw_videoport);
682 vp_stat |= DSS_IRQ_VP_SYNC_LOST(hw_videoport);
687 static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport)
691 if (vpstat & DSS_IRQ_VP_FRAME_DONE(hw_videoport))
693 if (vpstat & DSS_IRQ_VP_VSYNC_EVEN(hw_videoport))
695 if (vpstat & DSS_IRQ_VP_VSYNC_ODD(hw_videoport))
697 if (vpstat & DSS_IRQ_VP_SYNC_LOST(hw_videoport))
724 u32 hw_videoport)
726 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS);
728 return dispc_vp_irq_from_raw(stat, hw_videoport);
732 u32 hw_videoport, dispc_irq_t vpstat)
734 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
736 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
756 u32 hw_videoport)
758 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE);
760 return dispc_vp_irq_from_raw(stat, hw_videoport);
764 u32 hw_videoport, dispc_irq_t vpstat)
766 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
768 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);
842 u32 hw_videoport)
844 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport));
846 return dispc_vp_irq_from_raw(stat, hw_videoport);
850 u32 hw_videoport, dispc_irq_t vpstat)
852 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
854 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat);
876 u32 hw_videoport)
878 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport));
880 return dispc_vp_irq_from_raw(stat, hw_videoport);
884 u32 hw_videoport, dispc_irq_t vpstat)
886 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
888 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat);
1063 u32 hw_videoport,
1076 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
1082 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1090 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI_AM65X &&
1093 __func__, dispc->feat->vp_name[hw_videoport]);
1120 u32 hw_videoport, int num_lines)
1142 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
1145 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_videoport,
1149 u32 oldi_reset_bit = BIT(5 + hw_videoport);
1171 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
1182 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
1188 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1194 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X) {
1197 dispc_enable_am65x_oldi(dispc, hw_videoport, fmt);
1201 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
1210 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1216 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
1226 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
1231 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
1253 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X)
1256 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
1265 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1269 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1272 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
1274 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
1277 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
1279 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X) {
1280 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
1286 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
1288 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
1291 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
1293 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
1294 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
1338 u32 hw_videoport, u32 default_color)
1344 dispc_ovr_write(dispc, hw_videoport,
1346 dispc_ovr_write(dispc, hw_videoport,
1351 u32 hw_videoport,
1358 bus_type = dispc->feat->vp_bus_type[hw_videoport];
1424 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport)
1426 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]);
1435 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
1437 clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
1451 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
1457 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
1460 hw_videoport, rate);
1464 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]);
1469 hw_videoport, new_rate, rate);
1472 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
1479 u32 hw_plane, u32 hw_videoport,
1488 u32 hw_plane, u32 hw_videoport,
1493 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1495 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1497 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1502 u32 hw_plane, u32 hw_videoport,
1507 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1509 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1511 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1516 u32 hw_videoport, u32 x, u32 y, u32 layer)
1520 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
1527 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
1531 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,
1541 u32 hw_videoport, u32 layer, bool enable)
1546 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
2161 u32 hw_videoport)
2232 u32 hw_videoport)
2482 u32 hw_videoport)
2484 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2488 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2498 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
2504 u32 hw_videoport)
2506 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2510 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2520 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2525 u32 hw_videoport)
2527 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2531 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2542 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2547 u32 hw_videoport)
2551 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
2557 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
2560 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport);
2574 u32 hw_videoport,
2578 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2583 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n",
2584 __func__, hw_videoport, length, hwlen);
2620 dispc_vp_write_gamma_table(dispc, hw_videoport);
2667 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2680 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
2684 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2693 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
2697 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2732 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2746 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
2750 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2759 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
2763 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2768 u32 hw_videoport,
2784 dispc_vp_set_gamma(dispc, hw_videoport, lut, length);
2790 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
2792 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
2795 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
2798 dispc_vp_set_default_color(dispc, hw_videoport, 0);
2799 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset);