Lines Matching refs:tx_pu_value
46 u8 tx_pu_value; member
66 .tx_pu_value = 0x10,
81 .tx_pu_value = 0x40,
96 .tx_pu_value = 0x66,
111 .tx_pu_value = 0x66,
126 .tx_pu_value = 0x66,
145 .tx_pu_value = 0x40,
160 .tx_pu_value = 0x66,
175 .tx_pu_value = 0x66,
190 .tx_pu_value = 0x66,
210 .tx_pu_value = 0,
225 .tx_pu_value = 0,
240 .tx_pu_value = 0x66 /* 0 */,
255 .tx_pu_value = 64,
270 .tx_pu_value = 96,
289 .tx_pu_value = 0,
304 .tx_pu_value = 0,
319 .tx_pu_value = 0x66 /* 0 */,
334 .tx_pu_value = 64,
349 .tx_pu_value = 96,
2537 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()