Lines Matching +full:aux +full:- +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
408 struct tegra_output output;
427 struct drm_dp_aux *aux;
481 static inline struct tegra_sor *to_sor(struct tegra_output *output)
483 return container_of(output, struct tegra_sor, output);
488 u32 value = readl(sor->regs + (offset << 2));
490 trace_sor_readl(sor->dev, offset, value);
498 trace_sor_writel(sor->dev, offset, value);
499 writel(value, sor->regs + (offset << 2));
506 clk_disable_unprepare(sor->clk);
508 err = clk_set_parent(sor->clk_out, parent);
512 err = clk_prepare_enable(sor->clk);
535 * Implementing ->set_parent() here isn't really required because the parent
545 struct tegra_sor *sor = pad->sor;
569 struct tegra_sor *sor = pad->sor;
603 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
605 return ERR_PTR(-ENOMEM);
607 pad->sor = sor;
611 init.parent_names = tegra_clk_sor_pad_parents[sor->index];
612 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
615 pad->hw.init = &init;
617 clk = devm_clk_register(sor->dev, &pad->hw);
624 struct drm_dp_link *link = &sor->link;
628 for (i = 0; i < link->num_rates; i++) {
629 switch (link->rates[i]) {
637 link->rates[i]);
638 link->rates[i] = 0;
655 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
658 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
661 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
662 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
665 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
667 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
670 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
672 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
692 return -ETIMEDOUT;
703 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
724 return -ETIMEDOUT;
733 /* pre-charge all used lanes */
734 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
737 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
740 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
741 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
744 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
746 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
749 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
751 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
757 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
767 /* enable pad calibration logic */
768 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
779 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
786 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
799 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
808 const struct tegra_sor_soc *soc = sor->soc;
812 for (value = 0, i = 0; i < link->lanes; i++) {
813 u8 vs = link->train.request.voltage_swing[i];
814 u8 pe = link->train.request.pre_emphasis[i];
815 u8 pc = link->train.request.post_cursor[i];
816 u8 shift = sor->soc->lane_map[i] << 3;
818 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
819 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
820 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
822 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
823 tx_pu = sor->soc->tx_pu[pc][vs][pe];
825 switch (link->train.pattern) {
847 return -EINVAL;
850 if (link->caps.channel_coding)
859 if (link->caps.tps3_supported)
864 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
882 rate = drm_dp_link_rate_to_bw_code(link->rate);
883 lanes = link->lanes;
895 if (link->caps.enhanced_framing)
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
925 if (link->edp == 0)
934 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
938 /* power up and pre-charge lanes */
941 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
996 return -ETIMEDOUT;
1026 return -ETIMEDOUT;
1046 return -ETIMEDOUT;
1067 return -ETIMEDOUT;
1073 /* ratio between input and output */
1091 const u64 f = params->precision;
1094 active_sym = params->ratio * tu_size;
1096 frac = active_sym - active_count;
1101 frac = f - frac;
1124 approx = active_count + (active_frac * (f - 1)) * f;
1136 error = div_s64(active_sym - approx, tu_size);
1137 error *= params->num_clocks;
1139 if (error <= 0 && abs(error) < params->error) {
1140 params->active_count = div_u64(active_count, f);
1141 params->active_polarity = active_polarity;
1142 params->active_frac = active_frac;
1143 params->error = abs(error);
1144 params->tu_size = tu_size;
1158 const u64 f = 100000, link_rate = link->rate * 1000;
1159 const u64 pclk = (u64)mode->clock * 1000;
1160 u64 input, output, watermark, num;
1165 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1166 return -EINVAL;
1168 input = pclk * config->bits_per_pixel;
1169 output = link_rate * 8 * link->lanes;
1171 if (input >= output)
1172 return -ERANGE;
1175 params.ratio = div64_u64(input * f, output);
1176 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1181 for (i = params.tu_size; i >= 32; i--)
1186 config->active_polarity = 0;
1187 config->active_count = params.active_count;
1190 config->active_count--;
1192 config->tu_size = params.tu_size;
1193 config->active_frac = 1;
1195 config->active_polarity = params.active_polarity;
1196 config->active_count = params.active_count;
1197 config->active_frac = params.active_frac;
1198 config->tu_size = params.tu_size;
1201 dev_dbg(sor->dev,
1203 config->active_polarity, config->active_count,
1204 config->tu_size, config->active_frac);
1206 watermark = params.ratio * config->tu_size * (f - params.ratio);
1210 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1211 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1212 (link->lanes * 8);
1214 if (config->watermark > 30) {
1215 config->watermark = 30;
1216 dev_err(sor->dev,
1218 config->watermark);
1219 } else if (config->watermark > num_syms_per_line) {
1220 config->watermark = num_syms_per_line;
1221 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1222 config->watermark);
1226 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1227 config->hblank_symbols = div_u64(num, pclk);
1229 if (link->caps.enhanced_framing)
1230 config->hblank_symbols -= 3;
1232 config->hblank_symbols -= 12 / link->lanes;
1235 num = (mode->hdisplay - 25) * link_rate;
1236 config->vblank_symbols = div_u64(num, pclk);
1237 config->vblank_symbols -= 36 / link->lanes + 4;
1239 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1240 config->vblank_symbols);
1252 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1257 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1265 if (config->active_polarity)
1276 value |= config->hblank_symbols & 0xffff;
1281 value |= config->vblank_symbols & 0xffff;
1289 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1299 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1301 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1304 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1307 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1310 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1313 switch (state->bpc) {
1346 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1349 /* sync end = sync width - 1 */
1350 vse = mode->vsync_end - mode->vsync_start - 1;
1351 hse = mode->hsync_end - mode->hsync_start - 1;
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1357 vbe = vse + (mode->vtotal - mode->vsync_end);
1358 hbe = hse + (mode->htotal - mode->hsync_end);
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1364 vbs = vbe + mode->vdisplay;
1365 hbs = hbe + mode->hdisplay;
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1371 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1393 return -ETIMEDOUT;
1418 return -ETIMEDOUT;
1444 return -ETIMEDOUT;
1447 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1449 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1487 return -ETIMEDOUT;
1492 struct drm_info_node *node = s->private;
1493 struct tegra_sor *sor = node->info_ent->data;
1494 struct drm_crtc *crtc = sor->output.encoder.crtc;
1495 struct drm_device *drm = node->minor->dev;
1501 if (!crtc || !crtc->state->active) {
1502 err = -EBUSY;
1654 struct drm_info_node *node = s->private;
1655 struct tegra_sor *sor = node->info_ent->data;
1656 struct drm_crtc *crtc = sor->output.encoder.crtc;
1657 struct drm_device *drm = node->minor->dev;
1663 if (!crtc || !crtc->state->active) {
1664 err = -EBUSY;
1671 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1687 struct tegra_output *output = connector_to_output(connector);
1689 struct drm_minor *minor = connector->dev->primary;
1690 struct dentry *root = connector->debugfs_entry;
1691 struct tegra_sor *sor = to_sor(output);
1693 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1695 if (!sor->debugfs_files)
1696 return -ENOMEM;
1699 sor->debugfs_files[i].data = sor;
1701 drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1708 struct tegra_output *output = connector_to_output(connector);
1710 struct tegra_sor *sor = to_sor(output);
1712 drm_debugfs_remove_files(sor->debugfs_files, count,
1713 connector->debugfs_entry,
1714 connector->dev->primary);
1715 kfree(sor->debugfs_files);
1716 sor->debugfs_files = NULL;
1727 if (connector->state) {
1728 __drm_atomic_helper_connector_destroy_state(connector->state);
1729 kfree(connector->state);
1732 __drm_atomic_helper_connector_reset(connector, &state->base);
1738 struct tegra_output *output = connector_to_output(connector);
1739 struct tegra_sor *sor = to_sor(output);
1741 if (sor->aux)
1742 return drm_dp_aux_detect(sor->aux);
1750 struct tegra_sor_state *state = to_sor_state(connector->state);
1757 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1759 return ©->base;
1775 struct tegra_output *output = connector_to_output(connector);
1776 struct tegra_sor *sor = to_sor(output);
1779 if (sor->aux)
1780 drm_dp_aux_enable(sor->aux);
1784 if (sor->aux)
1785 drm_dp_aux_disable(sor->aux);
1807 struct tegra_output *output = encoder_to_output(encoder);
1809 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1810 unsigned long pclk = crtc_state->mode.clock * 1000;
1811 struct tegra_sor *sor = to_sor(output);
1815 info = &output->connector.display_info;
1822 state->link_speed = 20;
1823 state->pclk = pclk / 2;
1825 state->link_speed = 10;
1826 state->pclk = pclk;
1829 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1832 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1836 switch (info->bpc) {
1839 state->bpc = info->bpc;
1843 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1844 state->bpc = 8;
1856 for (i = size; i > 0; i--)
1857 value = (value << 8) | ptr[i - 1];
1884 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1897 * - subpack_low: bytes 0 - 3
1898 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1901 size_t rem = size - i, num = min_t(size_t, rem, 4);
1906 num = min_t(size_t, rem - num, 3);
1930 &sor->output.connector, mode);
1932 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1938 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1944 /* enable AVI infoframe */
1955 size_t length = drm_eld_size(sor->output.connector.eld), i;
1958 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1976 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2008 if (sor->format.channels != 2)
2017 /* enable advertising HBR capability */
2030 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2034 frame.channels = sor->format.channels;
2038 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2065 /* enable HW CTS */
2073 /* reset N counter and enable lookup */
2077 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2090 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2094 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2098 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2128 for (i = 0; i < sor->num_settings; i++)
2129 if (frequency <= sor->settings[i].frequency)
2130 return &sor->settings[i];
2147 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false);
2148 drm_scdc_set_scrambling(&sor->output.connector, false);
2155 if (sor->scdc_enabled) {
2156 cancel_delayed_work_sync(&sor->scdc);
2173 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true);
2174 drm_scdc_set_scrambling(&sor->output.connector, true);
2183 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) {
2188 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2193 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2196 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2198 if (mode->clock >= 340000 && scdc->supported) {
2199 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2201 sor->scdc_enabled = true;
2207 struct tegra_output *output = encoder_to_output(encoder);
2208 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2209 struct tegra_sor *sor = to_sor(output);
2218 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2226 if (!sor->soc->has_nvdisplay)
2229 value &= ~SOR_ENABLE(sor->index);
2237 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2239 err = tegra_io_pad_power_disable(sor->pad);
2241 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2243 host1x_client_suspend(&sor->client);
2248 struct tegra_output *output = encoder_to_output(encoder);
2250 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2252 struct tegra_sor *sor = to_sor(output);
2260 state = to_sor_state(output->connector.state);
2261 mode = &encoder->crtc->state->adjusted_mode;
2262 pclk = mode->clock * 1000;
2264 err = host1x_client_resume(&sor->client);
2266 dev_err(sor->dev, "failed to resume: %d\n", err);
2271 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2273 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2277 div = clk_get_rate(sor->clk) / 1000000 * 4;
2279 err = tegra_io_pad_power_enable(sor->pad);
2281 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2313 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2342 if (mode->clock < 340000) {
2377 if (!sor->soc->has_nvdisplay) {
2385 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2398 err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2400 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2407 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2409 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2414 /* switch the output clock to the parent pixel clock */
2415 err = clk_set_parent(sor->clk, sor->clk_parent);
2417 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2423 rate = clk_get_rate(sor->clk_parent);
2425 if (mode->clock >= 340000)
2430 clk_set_rate(sor->clk, rate);
2432 if (!sor->soc->has_nvdisplay) {
2433 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2436 if (mode->clock < 75000)
2442 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2448 if (!dc->soc->has_nvdisplay) {
2451 (mode->hsync_end - mode->hsync_start) +
2452 (mode->htotal - mode->hsync_end) - 10;
2469 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2481 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2486 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2488 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2489 mode->clock * 1000);
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2497 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2498 value |= SOR_PLL0_FILTER(settings->filter);
2499 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2503 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2506 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2507 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2516 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2517 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2518 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2519 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2522 value = settings->drive_current[3] << 24 |
2523 settings->drive_current[2] << 16 |
2524 settings->drive_current[1] << 8 |
2525 settings->drive_current[0] << 0;
2528 value = settings->preemphasis[3] << 24 |
2529 settings->preemphasis[2] << 16 |
2530 settings->preemphasis[1] << 8 |
2531 settings->preemphasis[0] << 0;
2534 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2537 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2540 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2542 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2546 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2550 if (!dc->soc->has_nvdisplay) {
2560 switch (state->bpc) {
2578 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2588 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2593 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2595 /* configure dynamic range of output */
2596 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2602 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2618 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2620 /* enable display to SOR clock and generate HDMI preamble */
2623 if (!sor->soc->has_nvdisplay)
2626 value |= SOR_ENABLE(sor->index);
2630 if (dc->soc->has_nvdisplay) {
2631 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2634 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2641 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2649 .enable = tegra_sor_hdmi_enable,
2655 struct tegra_output *output = encoder_to_output(encoder);
2656 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2657 struct tegra_sor *sor = to_sor(output);
2661 if (output->panel)
2662 drm_panel_disable(output->panel);
2666 * the AUX transactions would just be timing out.
2668 if (output->connector.status != connector_status_disconnected) {
2669 err = drm_dp_link_power_down(sor->aux, &sor->link);
2671 dev_err(sor->dev, "failed to power down link: %d\n",
2677 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2683 value &= ~SOR_ENABLE(sor->index);
2695 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2697 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2701 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2703 err = tegra_io_pad_power_disable(sor->pad);
2705 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2707 err = drm_dp_aux_disable(sor->aux);
2709 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2711 if (output->panel)
2712 drm_panel_unprepare(output->panel);
2714 host1x_client_suspend(&sor->client);
2719 struct tegra_output *output = encoder_to_output(encoder);
2720 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2721 struct tegra_sor *sor = to_sor(output);
2730 state = to_sor_state(output->connector.state);
2731 mode = &encoder->crtc->state->adjusted_mode;
2732 info = &output->connector.display_info;
2734 err = host1x_client_resume(&sor->client);
2736 dev_err(sor->dev, "failed to resume: %d\n", err);
2741 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2743 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2745 err = tegra_io_pad_power_enable(sor->pad);
2747 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2751 err = drm_dp_aux_enable(sor->aux);
2753 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2755 err = drm_dp_link_probe(sor->aux, &sor->link);
2757 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2761 err = drm_dp_link_choose(&sor->link, mode, info);
2763 dev_err(sor->dev, "failed to choose link: %d\n", err);
2765 if (output->panel)
2766 drm_panel_prepare(output->panel);
2768 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2778 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2782 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2789 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2797 if (output->panel)
2808 if (output->panel)
2819 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2829 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2842 err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2844 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2851 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2853 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2858 /* switch the output clock to the parent pixel clock */
2859 err = clk_set_parent(sor->clk, sor->clk_parent);
2861 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2866 /* use DP-A protocol */
2872 /* enable port */
2879 err = drm_dp_link_train(&sor->link);
2881 dev_err(sor->dev, "link training failed: %d\n", err);
2883 dev_dbg(sor->dev, "link training succeeded\n");
2885 err = drm_dp_link_power_up(sor->aux, &sor->link);
2887 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2891 config.bits_per_pixel = state->bpc * 3;
2893 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2895 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2900 if (output->panel) {
2909 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2916 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2921 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2924 value |= SOR_ENABLE(sor->index);
2931 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2933 if (output->panel)
2934 drm_panel_enable(output->panel);
2939 .enable = tegra_sor_dp_enable,
2958 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2965 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2966 if (IS_ERR(sor->avdd_io_supply))
2967 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply),
2970 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2972 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2977 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2978 if (IS_ERR(sor->vdd_pll_supply))
2979 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply),
2982 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2984 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2989 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2990 if (IS_ERR(sor->hdmi_supply))
2991 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply),
2994 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
2996 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3000 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3016 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3017 if (IS_ERR(sor->avdd_io_supply))
3018 return PTR_ERR(sor->avdd_io_supply);
3020 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3024 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3025 if (IS_ERR(sor->vdd_pll_supply))
3026 return PTR_ERR(sor->vdd_pll_supply);
3028 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3042 struct drm_device *drm = dev_get_drvdata(client->host);
3049 if (!sor->aux) {
3050 if (sor->ops == &tegra_sor_hdmi_ops) {
3054 } else if (sor->soc->supports_lvds) {
3059 if (sor->output.panel) {
3069 sor->link.ops = &tegra_sor_dp_link_ops;
3070 sor->link.aux = sor->aux;
3073 sor->output.dev = sor->dev;
3075 drm_connector_init_with_ddc(drm, &sor->output.connector,
3078 sor->output.ddc);
3079 drm_connector_helper_add(&sor->output.connector,
3081 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3083 drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3084 drm_encoder_helper_add(&sor->output.encoder, helpers);
3086 drm_connector_attach_encoder(&sor->output.connector,
3087 &sor->output.encoder);
3088 drm_connector_register(&sor->output.connector);
3090 err = tegra_output_init(drm, &sor->output);
3092 dev_err(client->dev, "failed to initialize output: %d\n", err);
3096 tegra_output_find_possible_crtcs(&sor->output, drm);
3098 if (sor->aux) {
3099 err = drm_dp_aux_attach(sor->aux, &sor->output);
3101 dev_err(sor->dev, "failed to attach DP: %d\n", err);
3107 * XXX: Remove this reset once proper hand-over from firmware to
3110 if (sor->rst) {
3111 err = pm_runtime_resume_and_get(sor->dev);
3113 dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3117 err = reset_control_acquire(sor->rst);
3119 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3124 err = reset_control_assert(sor->rst);
3126 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3132 err = clk_prepare_enable(sor->clk);
3134 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3140 if (sor->rst) {
3141 err = reset_control_deassert(sor->rst);
3143 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3145 clk_disable_unprepare(sor->clk);
3149 reset_control_release(sor->rst);
3150 pm_runtime_put(sor->dev);
3153 err = clk_prepare_enable(sor->clk_safe);
3155 clk_disable_unprepare(sor->clk);
3159 err = clk_prepare_enable(sor->clk_dp);
3161 clk_disable_unprepare(sor->clk_safe);
3162 clk_disable_unprepare(sor->clk);
3169 if (sor->rst)
3170 pm_runtime_put(sor->dev);
3180 tegra_output_exit(&sor->output);
3182 if (sor->aux) {
3183 err = drm_dp_aux_detach(sor->aux);
3185 dev_err(sor->dev, "failed to detach DP: %d\n", err);
3190 clk_disable_unprepare(sor->clk_safe);
3191 clk_disable_unprepare(sor->clk_dp);
3192 clk_disable_unprepare(sor->clk);
3200 struct device *dev = client->dev;
3203 if (sor->rst) {
3204 err = reset_control_assert(sor->rst);
3210 reset_control_release(sor->rst);
3215 clk_disable_unprepare(sor->clk);
3224 struct device *dev = client->dev;
3233 err = clk_prepare_enable(sor->clk);
3235 dev_err(dev, "failed to enable clock: %d\n", err);
3241 if (sor->rst) {
3242 err = reset_control_acquire(sor->rst);
3248 err = reset_control_deassert(sor->rst);
3258 reset_control_release(sor->rst);
3260 clk_disable_unprepare(sor->clk);
3630 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3631 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3632 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3633 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3634 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3635 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3642 struct device_node *np = sor->dev->of_node;
3648 if (sor->soc->has_nvdisplay) {
3653 sor->index = value;
3659 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3661 if (!sor->soc->supports_audio)
3662 sor->index = 0;
3664 sor->index = 1;
3667 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3669 /* fall back to default per-SoC XBAR configuration */
3671 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3675 sor->xbar_cfg[i] = xbar_cfg[i];
3697 tegra_hda_parse_format(format, &sor->format);
3699 if (sor->ops->audio_enable)
3700 sor->ops->audio_enable(sor);
3702 if (sor->ops->audio_disable)
3703 sor->ops->audio_disable(sor);
3716 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3718 return -ENOMEM;
3720 sor->soc = of_device_get_match_data(&pdev->dev);
3721 sor->output.dev = sor->dev = &pdev->dev;
3723 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3724 sor->soc->num_settings *
3725 sizeof(*sor->settings),
3727 if (!sor->settings)
3728 return -ENOMEM;
3730 sor->num_settings = sor->soc->num_settings;
3732 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3734 sor->aux = drm_dp_aux_find_by_of_node(np);
3737 if (!sor->aux)
3738 return -EPROBE_DEFER;
3740 if (get_device(sor->aux->dev))
3741 sor->output.ddc = &sor->aux->ddc;
3744 if (!sor->aux) {
3745 if (sor->soc->supports_hdmi) {
3746 sor->ops = &tegra_sor_hdmi_ops;
3747 sor->pad = TEGRA_IO_PAD_HDMI;
3748 } else if (sor->soc->supports_lvds) {
3749 dev_err(&pdev->dev, "LVDS not supported yet\n");
3750 return -ENODEV;
3752 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3753 return -ENODEV;
3756 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3763 sor->ops = &tegra_sor_dp_ops;
3764 sor->pad = TEGRA_IO_PAD_LVDS;
3771 err = tegra_output_probe(&sor->output);
3773 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3777 if (sor->ops && sor->ops->probe) {
3778 err = sor->ops->probe(sor);
3780 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3781 sor->ops->name, err);
3786 sor->regs = devm_platform_ioremap_resource(pdev, 0);
3787 if (IS_ERR(sor->regs)) {
3788 err = PTR_ERR(sor->regs);
3796 sor->irq = err;
3798 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3799 dev_name(sor->dev), sor);
3801 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3805 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3806 if (IS_ERR(sor->rst)) {
3807 err = PTR_ERR(sor->rst);
3809 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3810 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3821 sor->rst = NULL;
3824 sor->clk = devm_clk_get(&pdev->dev, NULL);
3825 if (IS_ERR(sor->clk)) {
3826 err = PTR_ERR(sor->clk);
3827 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3831 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3832 struct device_node *np = pdev->dev.of_node;
3840 if (of_property_match_string(np, "clock-names", "out") < 0)
3845 sor->clk_out = devm_clk_get(&pdev->dev, name);
3846 if (IS_ERR(sor->clk_out)) {
3847 err = PTR_ERR(sor->clk_out);
3848 dev_err(sor->dev, "failed to get %s clock: %d\n",
3854 sor->clk_out = sor->clk;
3857 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3858 if (IS_ERR(sor->clk_parent)) {
3859 err = PTR_ERR(sor->clk_parent);
3860 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3864 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3865 if (IS_ERR(sor->clk_safe)) {
3866 err = PTR_ERR(sor->clk_safe);
3867 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3871 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3872 if (IS_ERR(sor->clk_dp)) {
3873 err = PTR_ERR(sor->clk_dp);
3874 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3880 * the pad output clock, so we have to look it up from device tree.
3882 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3883 if (IS_ERR(sor->clk_pad)) {
3884 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3885 err = PTR_ERR(sor->clk_pad);
3890 * If the pad output clock is not available, then we assume
3894 sor->clk_pad = NULL;
3902 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3904 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3909 pm_runtime_enable(&pdev->dev);
3911 host1x_client_init(&sor->client);
3912 sor->client.ops = &sor_client_ops;
3913 sor->client.dev = &pdev->dev;
3917 * pad output clock.
3919 if (!sor->clk_pad) {
3922 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3923 sor->index);
3925 err = -ENOMEM;
3929 err = host1x_client_resume(&sor->client);
3931 dev_err(sor->dev, "failed to resume: %d\n", err);
3935 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3936 host1x_client_suspend(&sor->client);
3939 if (IS_ERR(sor->clk_pad)) {
3940 err = PTR_ERR(sor->clk_pad);
3941 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3946 err = __host1x_client_register(&sor->client);
3948 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3956 host1x_client_exit(&sor->client);
3957 pm_runtime_disable(&pdev->dev);
3959 if (sor->aux)
3960 sor->output.ddc = NULL;
3962 tegra_output_remove(&sor->output);
3964 if (sor->aux)
3965 put_device(sor->aux->dev);
3974 host1x_client_unregister(&sor->client);
3976 pm_runtime_disable(&pdev->dev);
3978 if (sor->aux) {
3979 put_device(sor->aux->dev);
3980 sor->output.ddc = NULL;
3983 tegra_output_remove(&sor->output);
3991 err = tegra_output_suspend(&sor->output);
3993 dev_err(dev, "failed to suspend output: %d\n", err);
3997 if (sor->hdmi_supply) {
3998 err = regulator_disable(sor->hdmi_supply);
4000 tegra_output_resume(&sor->output);
4013 if (sor->hdmi_supply) {
4014 err = regulator_enable(sor->hdmi_supply);
4019 err = tegra_output_resume(&sor->output);
4021 dev_err(dev, "failed to resume output: %d\n", err);
4023 if (sor->hdmi_supply)
4024 regulator_disable(sor->hdmi_supply);
4038 .name = "tegra-sor",