Lines Matching full:value
489 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
491 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
493 return value; in tegra_sor_readl()
496 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
499 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
500 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
547 u32 value; in tegra_clk_sor_pad_set_parent() local
549 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
550 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
554 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
558 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
562 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
572 u32 value; in tegra_clk_sor_pad_get_parent() local
574 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
576 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
650 u32 value; in tegra_sor_power_up_lanes() local
656 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
659 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
662 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
666 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
668 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
671 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
673 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
675 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
678 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()
680 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
685 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
686 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()
692 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()
701 u32 value; in tegra_sor_power_down_lanes() local
704 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
705 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down_lanes()
707 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
710 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down_lanes()
712 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
717 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
718 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()
724 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()
732 u32 value; in tegra_sor_dp_precharge() local
735 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
738 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
741 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
745 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
747 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
750 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
752 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
754 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
758 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
759 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_precharge()
761 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
766 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate() local
769 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
770 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
771 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
773 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
774 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_dp_term_calibrate()
775 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
780 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
781 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
782 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
783 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
787 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
788 if (value & SOR_PLL1_TERM_COMPOUT) in tegra_sor_dp_term_calibrate()
794 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
795 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
796 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
797 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
800 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
801 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
802 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
810 u32 pattern = 0, tx_pu = 0, value; in tegra_sor_dp_link_apply_training() local
813 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
828 value = SOR_DP_TPG_SCRAMBLER_GALIOS | in tegra_sor_dp_link_apply_training()
833 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
838 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
843 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
852 value |= SOR_DP_TPG_CHANNEL_CODING; in tegra_sor_dp_link_apply_training()
854 pattern = pattern << 8 | value; in tegra_sor_dp_link_apply_training()
865 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
866 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_link_apply_training()
867 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_link_apply_training()
868 value |= SOR_DP_PADCTL_TX_PU(tx_pu); in tegra_sor_dp_link_apply_training()
869 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
880 u32 value; in tegra_sor_dp_link_configure() local
887 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
888 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_dp_link_configure()
889 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_dp_link_configure()
890 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
892 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
893 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_dp_link_configure()
894 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_dp_link_configure()
897 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_dp_link_configure()
899 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
904 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
905 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_dp_link_configure()
909 value |= SOR_PLL1_LOADADJ(0x3); in tegra_sor_dp_link_configure()
913 value |= SOR_PLL1_LOADADJ(0x4); in tegra_sor_dp_link_configure()
917 value |= SOR_PLL1_LOADADJ(0x6); in tegra_sor_dp_link_configure()
921 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
924 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
927 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
929 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
931 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
973 u32 value; in tegra_sor_setup_pwm() local
975 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
976 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
977 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
978 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
980 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
981 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
982 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
983 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
984 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
985 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
990 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
991 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
1002 unsigned long value, timeout; in tegra_sor_attach() local
1005 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1006 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
1007 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
1008 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1012 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1013 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
1014 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1020 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1021 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
1032 unsigned long value, timeout; in tegra_sor_wakeup() local
1038 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1039 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
1041 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
1052 u32 value; in tegra_sor_power_up() local
1054 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1055 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
1056 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1061 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1062 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
1249 u32 value; in tegra_sor_apply_config() local
1251 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1252 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
1253 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1254 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1256 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1257 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
1258 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1260 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
1261 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1263 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
1264 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1267 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1269 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1271 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
1272 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
1273 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1275 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1276 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1277 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1278 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1280 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1281 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1282 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1283 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1292 u32 value; in tegra_sor_mode_set() local
1294 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1295 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
1296 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
1297 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
1299 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
1303 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1306 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1309 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1312 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1316 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
1320 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
1324 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1328 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1332 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1336 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1340 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1347 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1348 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1354 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1355 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1361 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1362 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1368 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1369 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1377 unsigned long value, timeout; in tegra_sor_detach() local
1380 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1381 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1382 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1388 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1389 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1393 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1397 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1398 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1399 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1403 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1404 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1405 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1411 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1412 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1418 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1426 unsigned long value, timeout; in tegra_sor_power_down() local
1429 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1430 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1431 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1432 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1437 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1438 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1444 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1454 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1455 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1456 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1462 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1464 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1465 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1466 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1467 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1476 u32 value; in tegra_sor_crc_wait() local
1481 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1482 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1498 u32 value; in tegra_sor_show_crc() local
1507 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1508 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1509 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1511 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1512 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1513 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1515 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1516 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1517 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1524 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1526 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1854 u32 value = 0; in tegra_sor_hdmi_subpack() local
1858 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1860 return value; in tegra_sor_hdmi_subpack()
1869 u32 value; in tegra_sor_hdmi_write_infopack() local
1890 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1893 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1904 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
1905 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1909 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
1910 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1920 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
1924 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1925 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
1926 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
1927 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1928 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1946 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1947 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1948 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1949 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1974 u32 value; in tegra_sor_audio_prepare() local
1981 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; in tegra_sor_audio_prepare()
1982 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1983 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1987 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; in tegra_sor_audio_prepare()
1988 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
2000 u32 value; in tegra_sor_audio_enable() local
2002 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2005 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); in tegra_sor_audio_enable()
2006 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); in tegra_sor_audio_enable()
2010 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2012 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2014 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; in tegra_sor_audio_enable()
2016 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2026 u32 value; in tegra_sor_hdmi_enable_audio_infoframe() local
2045 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2046 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2047 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2048 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2055 u32 value; in tegra_sor_hdmi_audio_enable() local
2061 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | in tegra_sor_hdmi_audio_enable()
2064 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2067 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2068 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2071 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; in tegra_sor_hdmi_audio_enable()
2072 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2075 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; in tegra_sor_hdmi_audio_enable()
2076 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2078 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2079 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2091 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2092 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2095 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2096 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2099 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2100 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2103 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2104 value &= ~SOR_HDMI_AUDIO_N_RESET; in tegra_sor_hdmi_audio_enable()
2105 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2112 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2114 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2115 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2116 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2138 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2140 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2141 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2142 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2143 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2164 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2166 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2167 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2168 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2169 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2211 u32 value; in tegra_sor_hdmi_disable() local
2225 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2228 value &= ~SOR1_TIMING_CYA; in tegra_sor_hdmi_disable()
2230 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2258 u32 value; in tegra_sor_hdmi_enable() local
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2287 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2293 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2297 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2298 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2302 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2308 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2309 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2310 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2314 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2315 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2317 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2320 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2321 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2327 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2329 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2332 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2333 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2339 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2340 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2341 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2345 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2348 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2351 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2352 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2357 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2358 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2359 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2360 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2362 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2363 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2364 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2365 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2366 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2367 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2369 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2371 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2373 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2376 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2380 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2381 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2385 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2386 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2390 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2434 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2438 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2440 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2445 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2447 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2455 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2457 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2459 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2462 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2463 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2464 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2476 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2477 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2478 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2479 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2482 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2495 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2496 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2497 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2499 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2500 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2504 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2505 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2506 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2507 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2508 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2509 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2510 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2513 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2514 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2515 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2516 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2519 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2520 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2523 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2527 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2529 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2533 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2535 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2536 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2537 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2538 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2539 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2541 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2542 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2543 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2544 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2547 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2548 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2553 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2554 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2557 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2558 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2559 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2563 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2567 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2571 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2575 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2580 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2584 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2587 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2588 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2589 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2590 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2597 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2598 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2599 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2600 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2603 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2604 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2605 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2606 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2613 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2614 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2615 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2622 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2625 value |= SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2627 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2629 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2632 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2633 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2634 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2659 u32 value; in tegra_sor_dp_disable() local
2683 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2684 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2688 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2689 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_disable()
2690 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; in tegra_sor_dp_disable()
2691 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_dp_disable()
2692 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2728 u32 value; in tegra_sor_dp_enable() local
2769 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2770 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_dp_enable()
2771 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2776 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2780 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); in tegra_sor_dp_enable()
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2784 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_dp_enable()
2785 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_dp_enable()
2786 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2790 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2791 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_dp_enable()
2792 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_dp_enable()
2793 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2795 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2796 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_dp_enable()
2799 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_dp_enable()
2801 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; in tegra_sor_dp_enable()
2803 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2807 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2810 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2812 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2814 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_enable()
2815 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2821 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_dp_enable()
2822 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_dp_enable()
2823 value |= SOR_PLL0_ICHPMP(0x1); in tegra_sor_dp_enable()
2824 value |= SOR_PLL0_VCOCAP(0x3); in tegra_sor_dp_enable()
2825 value |= SOR_PLL0_RESISTOR_EXT; in tegra_sor_dp_enable()
2826 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2829 for (value = 0, i = 0; i < 5; i++) in tegra_sor_dp_enable()
2830 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2834 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2868 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2869 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_enable()
2870 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_dp_enable()
2871 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2874 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2875 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_dp_enable()
2876 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2903 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_dp_enable()
2905 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2924 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
2925 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2926 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
3646 u32 value; in tegra_sor_parse_dt() local
3650 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
3654 sor->index = value; in tegra_sor_parse_dt()
3685 u32 value; in tegra_sor_irq() local
3687 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3688 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3690 if (value & SOR_INT_CODEC_SCRATCH0) { in tegra_sor_irq()
3691 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3693 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { in tegra_sor_irq()
3696 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; in tegra_sor_irq()