Lines Matching +full:0 +full:x3a
37 #define SOR_REKEY 0x38
62 .vcocap = 0x0,
63 .filter = 0x0,
64 .ichpmp = 0x1,
65 .loadadj = 0x3,
66 .tmds_termadj = 0x9,
67 .tx_pu_value = 0x10,
68 .bg_temp_coef = 0x3,
69 .bg_vref_level = 0x8,
70 .avdd10_level = 0x4,
71 .avdd14_level = 0x4,
72 .sparepll = 0x0,
73 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
74 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
77 .vcocap = 0x3,
78 .filter = 0x0,
79 .ichpmp = 0x1,
80 .loadadj = 0x3,
81 .tmds_termadj = 0x9,
82 .tx_pu_value = 0x40,
83 .bg_temp_coef = 0x3,
84 .bg_vref_level = 0x8,
85 .avdd10_level = 0x4,
86 .avdd14_level = 0x4,
87 .sparepll = 0x0,
88 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
89 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
92 .vcocap = 0x3,
93 .filter = 0x0,
94 .ichpmp = 0x1,
95 .loadadj = 0x3,
96 .tmds_termadj = 0x9,
97 .tx_pu_value = 0x66,
98 .bg_temp_coef = 0x3,
99 .bg_vref_level = 0x8,
100 .avdd10_level = 0x4,
101 .avdd14_level = 0x4,
102 .sparepll = 0x0,
103 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
104 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
107 .vcocap = 0x3,
108 .filter = 0x0,
109 .ichpmp = 0x1,
110 .loadadj = 0x3,
111 .tmds_termadj = 0x9,
112 .tx_pu_value = 0x66,
113 .bg_temp_coef = 0x3,
114 .bg_vref_level = 0xa,
115 .avdd10_level = 0x4,
116 .avdd14_level = 0x4,
117 .sparepll = 0x0,
118 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
119 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
122 .vcocap = 0x3,
123 .filter = 0x0,
124 .ichpmp = 0x1,
125 .loadadj = 0x3,
126 .tmds_termadj = 0x9,
127 .tx_pu_value = 0x66,
128 .bg_temp_coef = 0x3,
129 .bg_vref_level = 0x8,
130 .avdd10_level = 0x4,
131 .avdd14_level = 0x4,
132 .sparepll = 0x0,
133 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
134 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
141 .vcocap = 0x3,
142 .filter = 0x0,
143 .ichpmp = 0x1,
144 .loadadj = 0x3,
145 .tmds_termadj = 0x9,
146 .tx_pu_value = 0x40,
147 .bg_temp_coef = 0x3,
148 .bg_vref_level = 0x8,
149 .avdd10_level = 0x4,
150 .avdd14_level = 0x4,
151 .sparepll = 0x0,
152 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
153 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
156 .vcocap = 0x3,
157 .filter = 0x0,
158 .ichpmp = 0x1,
159 .loadadj = 0x3,
160 .tmds_termadj = 0x9,
161 .tx_pu_value = 0x66,
162 .bg_temp_coef = 0x3,
163 .bg_vref_level = 0x8,
164 .avdd10_level = 0x4,
165 .avdd14_level = 0x4,
166 .sparepll = 0x0,
167 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
168 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
171 .vcocap = 0x3,
172 .filter = 0x0,
173 .ichpmp = 0x6,
174 .loadadj = 0x3,
175 .tmds_termadj = 0x9,
176 .tx_pu_value = 0x66,
177 .bg_temp_coef = 0x3,
178 .bg_vref_level = 0xf,
179 .avdd10_level = 0x4,
180 .avdd14_level = 0x4,
181 .sparepll = 0x0,
182 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
183 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
186 .vcocap = 0x3,
187 .filter = 0x0,
188 .ichpmp = 0xa,
189 .loadadj = 0x3,
190 .tmds_termadj = 0xb,
191 .tx_pu_value = 0x66,
192 .bg_temp_coef = 0x3,
193 .bg_vref_level = 0xe,
194 .avdd10_level = 0x4,
195 .avdd14_level = 0x4,
196 .sparepll = 0x0,
197 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
198 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
206 .vcocap = 0,
210 .tmds_termadj = 0xf,
211 .tx_pu_value = 0,
216 .sparepll = 0x54,
217 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
218 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
225 .tmds_termadj = 0xf,
226 .tx_pu_value = 0,
231 .sparepll = 0x44,
232 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
233 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
241 .tx_pu_value = 0x66 /* 0 */,
246 .sparepll = 0x00, /* 0x34 */
247 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
248 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
261 .sparepll = 0x34,
262 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
263 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
276 .sparepll = 0x34,
277 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
278 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
285 .vcocap = 0,
289 .tmds_termadj = 0xf,
290 .tx_pu_value = 0,
295 .sparepll = 0x54,
296 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
297 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
304 .tmds_termadj = 0xf,
305 .tx_pu_value = 0,
310 .sparepll = 0x44,
311 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
312 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
320 .tx_pu_value = 0x66 /* 0 */,
325 .sparepll = 0x00, /* 0x34 */
326 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
327 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
340 .sparepll = 0x34,
341 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
342 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
355 .sparepll = 0x34,
356 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
357 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
510 if (err < 0) in tegra_sor_set_parent_clock()
514 if (err < 0) in tegra_sor_set_parent_clock()
517 return 0; in tegra_sor_set_parent_clock()
553 case 0: in tegra_clk_sor_pad_set_parent()
564 return 0; in tegra_clk_sor_pad_set_parent()
579 parent = 0; in tegra_clk_sor_pad_get_parent()
611 init.flags = 0; in tegra_clk_sor_pad_register()
629 for (i = 0; i < link->num_rates; i++) { in tegra_sor_filter_rates()
639 link->rates[i] = 0; in tegra_sor_filter_rates()
670 if (lanes == 0) in tegra_sor_power_up_lanes()
671 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
673 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
686 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()
692 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()
695 return 0; in tegra_sor_power_up_lanes()
718 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()
724 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()
727 return 0; in tegra_sor_power_down_lanes()
749 if (lanes == 0) in tegra_sor_dp_precharge()
750 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
752 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
766 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate()
808 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; in tegra_sor_dp_link_apply_training()
810 u32 pattern = 0, tx_pu = 0, value; in tegra_sor_dp_link_apply_training()
813 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
873 return 0; in tegra_sor_dp_link_apply_training()
909 value |= SOR_PLL1_LOADADJ(0x3); in tegra_sor_dp_link_configure()
913 value |= SOR_PLL1_LOADADJ(0x4); in tegra_sor_dp_link_configure()
917 value |= SOR_PLL1_LOADADJ(0x6); in tegra_sor_dp_link_configure()
926 if (link->edp == 0) in tegra_sor_dp_link_configure()
934 if (err < 0) { in tegra_sor_dp_link_configure()
941 if (err < 0) { in tegra_sor_dp_link_configure()
949 return 0; in tegra_sor_dp_link_configure()
959 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
961 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
966 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
968 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
977 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
982 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
991 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
992 return 0; in tegra_sor_setup_pwm()
1021 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
1022 return 0; in tegra_sor_attach()
1042 return 0; in tegra_sor_wakeup()
1062 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
1063 return 0; in tegra_sor_power_up()
1091 u32 active_polarity, active_frac = 0; in tegra_sor_compute_params()
1104 active_polarity = 0; in tegra_sor_compute_params()
1107 if (frac != 0) { in tegra_sor_compute_params()
1121 active_polarity = 0; in tegra_sor_compute_params()
1140 if (error <= 0 && abs(error) < params->error) { in tegra_sor_compute_params()
1147 if (error == 0) in tegra_sor_compute_params()
1175 memset(¶ms, 0, sizeof(params)); in tegra_sor_compute_config()
1186 if (params.active_frac == 0) { in tegra_sor_compute_config()
1187 config->active_polarity = 0; in tegra_sor_compute_config()
1243 return 0; in tegra_sor_compute_config()
1277 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1282 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1347 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1354 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1361 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1368 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1372 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1393 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1412 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1418 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1421 return 0; in tegra_sor_detach()
1438 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1439 return 0; in tegra_sor_power_down()
1444 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1449 if (err < 0) { in tegra_sor_power_down()
1471 return 0; in tegra_sor_power_down()
1483 return 0; in tegra_sor_crc_wait()
1497 int err = 0; in tegra_sor_show_crc()
1520 if (err < 0) in tegra_sor_show_crc()
1541 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1543 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1545 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1547 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1549 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1551 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1570 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1660 int err = 0; in tegra_sor_show_regs()
1669 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { in tegra_sor_show_regs()
1682 { "crc", tegra_sor_show_crc, 0, NULL },
1683 { "regs", tegra_sor_show_regs, 0, NULL },
1699 for (i = 0; i < count; i++) in tegra_sor_late_register()
1704 return 0; in tegra_sor_late_register()
1831 pclk, 0); in tegra_sor_encoder_atomic_check()
1832 if (err < 0) { in tegra_sor_encoder_atomic_check()
1849 return 0; in tegra_sor_encoder_atomic_check()
1854 u32 value = 0; in tegra_sor_hdmi_subpack()
1857 for (i = size; i > 0; i--) in tegra_sor_hdmi_subpack()
1871 switch (ptr[0]) { in tegra_sor_hdmi_write_infopack()
1886 ptr[0]); in tegra_sor_hdmi_write_infopack()
1890 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1898 * - subpack_low: bytes 0 - 3 in tegra_sor_hdmi_write_infopack()
1899 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) in tegra_sor_hdmi_write_infopack()
1932 if (err < 0) { in tegra_sor_hdmi_setup_avi_infoframe()
1938 if (err < 0) { in tegra_sor_hdmi_setup_avi_infoframe()
1951 return 0; in tegra_sor_hdmi_setup_avi_infoframe()
1958 for (i = 0; i < length; i++) in tegra_sor_write_eld()
1969 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); in tegra_sor_write_eld()
1993 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_unprepare()
1994 tegra_sor_writel(sor, 0, SOR_INT_MASK); in tegra_sor_audio_unprepare()
1995 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); in tegra_sor_audio_unprepare()
2030 if (err < 0) { in tegra_sor_hdmi_enable_audio_infoframe()
2038 if (err < 0) { in tegra_sor_hdmi_enable_audio_infoframe()
2050 return 0; in tegra_sor_hdmi_enable_audio_infoframe()
2059 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); in tegra_sor_hdmi_audio_enable()
2067 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2129 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2218 if (err < 0) in tegra_sor_hdmi_disable()
2221 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2237 if (err < 0) in tegra_sor_hdmi_disable()
2241 if (err < 0) in tegra_sor_hdmi_disable()
2266 if (err < 0) { in tegra_sor_hdmi_enable()
2273 if (err < 0) { in tegra_sor_hdmi_enable()
2281 if (err < 0) in tegra_sor_hdmi_enable()
2321 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2333 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2369 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2385 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2389 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2398 #if 0 in tegra_sor_hdmi_enable()
2400 if (err < 0) { in tegra_sor_hdmi_enable()
2409 if (err < 0) { in tegra_sor_hdmi_enable()
2417 if (err < 0) { in tegra_sor_hdmi_enable()
2469 if (err < 0) in tegra_sor_hdmi_enable()
2526 settings->drive_current[0] << 0; in tegra_sor_hdmi_enable()
2532 settings->preemphasis[0] << 0; in tegra_sor_hdmi_enable()
2593 if (err < 0) in tegra_sor_hdmi_enable()
2618 if (err < 0) in tegra_sor_hdmi_enable()
2641 if (err < 0) in tegra_sor_hdmi_enable()
2671 if (err < 0) in tegra_sor_dp_disable()
2677 if (err < 0) in tegra_sor_dp_disable()
2680 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_dp_disable()
2697 if (err < 0) in tegra_sor_dp_disable()
2701 if (err < 0) in tegra_sor_dp_disable()
2705 if (err < 0) in tegra_sor_dp_disable()
2709 if (err < 0) in tegra_sor_dp_disable()
2736 if (err < 0) { in tegra_sor_dp_enable()
2743 if (err < 0) in tegra_sor_dp_enable()
2747 if (err < 0) in tegra_sor_dp_enable()
2753 if (err < 0) in tegra_sor_dp_enable()
2757 if (err < 0) in tegra_sor_dp_enable()
2763 if (err < 0) in tegra_sor_dp_enable()
2818 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_enable()
2823 value |= SOR_PLL0_ICHPMP(0x1); in tegra_sor_dp_enable()
2824 value |= SOR_PLL0_VCOCAP(0x3); in tegra_sor_dp_enable()
2829 for (value = 0, i = 0; i < 5; i++) in tegra_sor_dp_enable()
2833 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_dp_enable()
2842 #if 0 in tegra_sor_dp_enable()
2844 if (err < 0) { in tegra_sor_dp_enable()
2853 if (err < 0) { in tegra_sor_dp_enable()
2861 if (err < 0) { in tegra_sor_dp_enable()
2881 if (err < 0) in tegra_sor_dp_enable()
2887 if (err < 0) in tegra_sor_dp_enable()
2891 memset(&config, 0, sizeof(config)); in tegra_sor_dp_enable()
2895 if (err < 0) in tegra_sor_dp_enable()
2909 if (err < 0) in tegra_sor_dp_enable()
2916 if (err < 0) in tegra_sor_dp_enable()
2921 if (err < 0) in tegra_sor_dp_enable()
2931 if (err < 0) in tegra_sor_dp_enable()
2972 if (err < 0) { in tegra_sor_hdmi_probe()
2984 if (err < 0) { in tegra_sor_hdmi_probe()
2996 if (err < 0) { in tegra_sor_hdmi_probe()
3003 return 0; in tegra_sor_hdmi_probe()
3022 if (err < 0) in tegra_sor_dp_probe()
3030 if (err < 0) in tegra_sor_dp_probe()
3033 return 0; in tegra_sor_dp_probe()
3092 if (err < 0) { in tegra_sor_init()
3101 if (err < 0) { in tegra_sor_init()
3113 if (err < 0) { in tegra_sor_init()
3119 if (err < 0) { in tegra_sor_init()
3126 if (err < 0) { in tegra_sor_init()
3134 if (err < 0) { in tegra_sor_init()
3143 if (err < 0) { in tegra_sor_init()
3155 if (err < 0) { in tegra_sor_init()
3161 if (err < 0) { in tegra_sor_init()
3167 return 0; in tegra_sor_init()
3185 if (err < 0) { in tegra_sor_exit()
3195 return 0; in tegra_sor_exit()
3206 if (err < 0) { in tegra_sor_runtime_suspend()
3219 return 0; in tegra_sor_runtime_suspend()
3229 if (err < 0) { in tegra_sor_runtime_resume()
3235 if (err < 0) { in tegra_sor_runtime_resume()
3244 if (err < 0) { in tegra_sor_runtime_resume()
3250 if (err < 0) { in tegra_sor_runtime_resume()
3256 return 0; in tegra_sor_runtime_resume()
3275 0, 1, 2, 3, 4
3279 .head_state0 = 0x05,
3280 .head_state1 = 0x07,
3281 .head_state2 = 0x09,
3282 .head_state3 = 0x0b,
3283 .head_state4 = 0x0d,
3284 .head_state5 = 0x0f,
3285 .pll0 = 0x17,
3286 .pll1 = 0x18,
3287 .pll2 = 0x19,
3288 .pll3 = 0x1a,
3289 .dp_padctl0 = 0x5c,
3290 .dp_padctl2 = 0x73,
3293 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3295 2, 1, 0, 3,
3300 { 0x13, 0x19, 0x1e, 0x28 },
3301 { 0x1e, 0x25, 0x2d, },
3302 { 0x28, 0x32, },
3303 { 0x3c, },
3305 { 0x12, 0x17, 0x1b, 0x25 },
3306 { 0x1c, 0x23, 0x2a, },
3307 { 0x25, 0x2f, },
3308 { 0x39, }
3310 { 0x12, 0x16, 0x1a, 0x22 },
3311 { 0x1b, 0x20, 0x27, },
3312 { 0x24, 0x2d, },
3313 { 0x36, },
3315 { 0x11, 0x14, 0x17, 0x1f },
3316 { 0x19, 0x1e, 0x24, },
3317 { 0x22, 0x2a, },
3318 { 0x32, },
3324 { 0x00, 0x09, 0x13, 0x25 },
3325 { 0x00, 0x0f, 0x1e, },
3326 { 0x00, 0x14, },
3327 { 0x00, },
3329 { 0x00, 0x0a, 0x14, 0x28 },
3330 { 0x00, 0x0f, 0x1e, },
3331 { 0x00, 0x14, },
3332 { 0x00 },
3334 { 0x00, 0x0a, 0x14, 0x28 },
3335 { 0x00, 0x0f, 0x1e, },
3336 { 0x00, 0x14, },
3337 { 0x00, },
3339 { 0x00, 0x0a, 0x14, 0x28 },
3340 { 0x00, 0x0f, 0x1e, },
3341 { 0x00, 0x14, },
3342 { 0x00, },
3348 { 0x00, 0x00, 0x00, 0x00 },
3349 { 0x00, 0x00, 0x00, },
3350 { 0x00, 0x00, },
3351 { 0x00, },
3353 { 0x02, 0x02, 0x04, 0x05 },
3354 { 0x02, 0x04, 0x05, },
3355 { 0x04, 0x05, },
3356 { 0x05, },
3358 { 0x04, 0x05, 0x08, 0x0b },
3359 { 0x05, 0x09, 0x0b, },
3360 { 0x08, 0x0a, },
3361 { 0x0b, },
3363 { 0x05, 0x09, 0x0b, 0x12 },
3364 { 0x09, 0x0d, 0x12, },
3365 { 0x0b, 0x0f, },
3366 { 0x12, },
3372 { 0x20, 0x30, 0x40, 0x60 },
3373 { 0x30, 0x40, 0x60, },
3374 { 0x40, 0x60, },
3375 { 0x60, },
3377 { 0x20, 0x20, 0x30, 0x50 },
3378 { 0x30, 0x40, 0x50, },
3379 { 0x40, 0x50, },
3380 { 0x60, },
3382 { 0x20, 0x20, 0x30, 0x40, },
3383 { 0x30, 0x30, 0x40, },
3384 { 0x40, 0x50, },
3385 { 0x60, },
3387 { 0x20, 0x20, 0x20, 0x40, },
3388 { 0x30, 0x30, 0x40, },
3389 { 0x40, 0x40, },
3390 { 0x60, },
3412 { 0x00, 0x08, 0x12, 0x24 },
3413 { 0x01, 0x0e, 0x1d, },
3414 { 0x01, 0x13, },
3415 { 0x00, },
3417 { 0x00, 0x08, 0x12, 0x24 },
3418 { 0x00, 0x0e, 0x1d, },
3419 { 0x00, 0x13, },
3420 { 0x00 },
3422 { 0x00, 0x08, 0x12, 0x24 },
3423 { 0x00, 0x0e, 0x1d, },
3424 { 0x00, 0x13, },
3425 { 0x00, },
3427 { 0x00, 0x08, 0x12, 0x24 },
3428 { 0x00, 0x0e, 0x1d, },
3429 { 0x00, 0x13, },
3430 { 0x00, },
3451 .head_state0 = 0x05,
3452 .head_state1 = 0x07,
3453 .head_state2 = 0x09,
3454 .head_state3 = 0x0b,
3455 .head_state4 = 0x0d,
3456 .head_state5 = 0x0f,
3457 .pll0 = 0x17,
3458 .pll1 = 0x18,
3459 .pll2 = 0x19,
3460 .pll3 = 0x1a,
3461 .dp_padctl0 = 0x5c,
3462 .dp_padctl2 = 0x73,
3466 2, 1, 0, 3, 4
3470 0, 1, 2, 3,
3512 .head_state0 = 0x151,
3513 .head_state1 = 0x154,
3514 .head_state2 = 0x157,
3515 .head_state3 = 0x15a,
3516 .head_state4 = 0x15d,
3517 .head_state5 = 0x160,
3518 .pll0 = 0x163,
3519 .pll1 = 0x164,
3520 .pll2 = 0x165,
3521 .pll3 = 0x166,
3522 .dp_padctl0 = 0x168,
3523 .dp_padctl2 = 0x16a,
3528 { 0x13, 0x19, 0x1e, 0x28 },
3529 { 0x1e, 0x25, 0x2d, },
3530 { 0x28, 0x32, },
3531 { 0x39, },
3533 { 0x12, 0x16, 0x1b, 0x25 },
3534 { 0x1c, 0x23, 0x2a, },
3535 { 0x25, 0x2f, },
3536 { 0x37, }
3538 { 0x12, 0x16, 0x1a, 0x22 },
3539 { 0x1b, 0x20, 0x27, },
3540 { 0x24, 0x2d, },
3541 { 0x35, },
3543 { 0x11, 0x14, 0x17, 0x1f },
3544 { 0x19, 0x1e, 0x24, },
3545 { 0x22, 0x2a, },
3546 { 0x32, },
3552 { 0x00, 0x08, 0x12, 0x24 },
3553 { 0x01, 0x0e, 0x1d, },
3554 { 0x01, 0x13, },
3555 { 0x00, },
3557 { 0x00, 0x08, 0x12, 0x24 },
3558 { 0x00, 0x0e, 0x1d, },
3559 { 0x00, 0x13, },
3560 { 0x00 },
3562 { 0x00, 0x08, 0x14, 0x24 },
3563 { 0x00, 0x0e, 0x1d, },
3564 { 0x00, 0x13, },
3565 { 0x00, },
3567 { 0x00, 0x08, 0x12, 0x24 },
3568 { 0x00, 0x0e, 0x1d, },
3569 { 0x00, 0x13, },
3570 { 0x00, },
3595 .head_state0 = 0x151,
3596 .head_state1 = 0x155,
3597 .head_state2 = 0x159,
3598 .head_state3 = 0x15d,
3599 .head_state4 = 0x161,
3600 .head_state5 = 0x165,
3601 .pll0 = 0x169,
3602 .pll1 = 0x16a,
3603 .pll2 = 0x16b,
3604 .pll3 = 0x16c,
3605 .dp_padctl0 = 0x16e,
3606 .dp_padctl2 = 0x16f,
3651 if (err < 0) in tegra_sor_parse_dt()
3663 sor->index = 0; in tegra_sor_parse_dt()
3669 if (err < 0) { in tegra_sor_parse_dt()
3671 for (i = 0; i < 5; i++) in tegra_sor_parse_dt()
3675 for (i = 0; i < 5; i++) in tegra_sor_parse_dt()
3679 return 0; in tegra_sor_parse_dt()
3733 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); in tegra_sor_probe()
3757 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); in tegra_sor_probe()
3769 if (err < 0) in tegra_sor_probe()
3773 if (err < 0) { in tegra_sor_probe()
3780 if (err < 0) { in tegra_sor_probe()
3787 sor->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_sor_probe()
3793 err = platform_get_irq(pdev, 0); in tegra_sor_probe()
3794 if (err < 0) in tegra_sor_probe()
3799 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3801 if (err < 0) { in tegra_sor_probe()
3841 if (of_property_match_string(np, "clock-names", "out") < 0) in tegra_sor_probe()
3904 if (err < 0) { in tegra_sor_probe()
3931 if (err < 0) { in tegra_sor_probe()
3948 if (err < 0) { in tegra_sor_probe()
3954 return 0; in tegra_sor_probe()
3993 if (err < 0) { in tegra_sor_suspend()
4000 if (err < 0) { in tegra_sor_suspend()
4006 return 0; in tegra_sor_suspend()
4016 if (err < 0) in tegra_sor_resume()
4021 if (err < 0) { in tegra_sor_resume()
4030 return 0; in tegra_sor_resume()