1 // SPDX-License-Identifier: GPL-2.0-only
91 static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)  in tegra_rgb_encoder_disable()  argument
93 	struct tegra_output *output = encoder_to_output(encoder);  in tegra_rgb_encoder_disable()
96 	tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));  in tegra_rgb_encoder_disable()
97 	tegra_dc_commit(rgb->dc);  in tegra_rgb_encoder_disable()
100 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)  in tegra_rgb_encoder_enable()  argument
102 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;  in tegra_rgb_encoder_enable()
103 	struct tegra_output *output = encoder_to_output(encoder);  in tegra_rgb_encoder_enable()
107 	tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));  in tegra_rgb_encoder_enable()
110 	tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);  in tegra_rgb_encoder_enable()
112 	/* configure H- and V-sync signal polarities */  in tegra_rgb_encoder_enable()
113 	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));  in tegra_rgb_encoder_enable()
115 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)  in tegra_rgb_encoder_enable()
120 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)  in tegra_rgb_encoder_enable()
125 	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));  in tegra_rgb_encoder_enable()
130 	tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);  in tegra_rgb_encoder_enable()
132 	tegra_dc_commit(rgb->dc);  in tegra_rgb_encoder_enable()
137 	if (!rgb->pll_d2_out0)  in tegra_rgb_pll_rate_change_allowed()
140 	if (!clk_is_match(rgb->clk_parent, rgb->pll_d_out0) &&  in tegra_rgb_pll_rate_change_allowed()
141 	    !clk_is_match(rgb->clk_parent, rgb->pll_d2_out0))  in tegra_rgb_pll_rate_change_allowed()
148 tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,  in tegra_rgb_encoder_atomic_check()  argument
152 	struct tegra_output *output = encoder_to_output(encoder);  in tegra_rgb_encoder_atomic_check()
153 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);  in tegra_rgb_encoder_atomic_check()
154 	unsigned long pclk = crtc_state->mode.clock * 1000;  in tegra_rgb_encoder_atomic_check()
183 		div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;  in tegra_rgb_encoder_atomic_check()
187 	err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,  in tegra_rgb_encoder_atomic_check()
190 		dev_err(output->dev, "failed to setup CRTC state: %d\n", err);  in tegra_rgb_encoder_atomic_check()
209 	np = of_get_child_by_name(dc->dev->of_node, "rgb");  in tegra_dc_rgb_probe()
211 		return -ENODEV;  in tegra_dc_rgb_probe()
213 	rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);  in tegra_dc_rgb_probe()
215 		return -ENOMEM;  in tegra_dc_rgb_probe()
217 	rgb->output.dev = dc->dev;  in tegra_dc_rgb_probe()
218 	rgb->output.of_node = np;  in tegra_dc_rgb_probe()
219 	rgb->dc = dc;  in tegra_dc_rgb_probe()
221 	err = tegra_output_probe(&rgb->output);  in tegra_dc_rgb_probe()
225 	rgb->clk = devm_clk_get(dc->dev, NULL);  in tegra_dc_rgb_probe()
226 	if (IS_ERR(rgb->clk)) {  in tegra_dc_rgb_probe()
227 		dev_err(dc->dev, "failed to get clock\n");  in tegra_dc_rgb_probe()
228 		err = PTR_ERR(rgb->clk);  in tegra_dc_rgb_probe()
232 	rgb->clk_parent = devm_clk_get(dc->dev, "parent");  in tegra_dc_rgb_probe()
233 	if (IS_ERR(rgb->clk_parent)) {  in tegra_dc_rgb_probe()
234 		dev_err(dc->dev, "failed to get parent clock\n");  in tegra_dc_rgb_probe()
235 		err = PTR_ERR(rgb->clk_parent);  in tegra_dc_rgb_probe()
239 	err = clk_set_parent(rgb->clk, rgb->clk_parent);  in tegra_dc_rgb_probe()
241 		dev_err(dc->dev, "failed to set parent clock: %d\n", err);  in tegra_dc_rgb_probe()
245 	rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0");  in tegra_dc_rgb_probe()
246 	if (IS_ERR(rgb->pll_d_out0)) {  in tegra_dc_rgb_probe()
247 		err = PTR_ERR(rgb->pll_d_out0);  in tegra_dc_rgb_probe()
248 		dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err);  in tegra_dc_rgb_probe()
252 	if (dc->soc->has_pll_d2_out0) {  in tegra_dc_rgb_probe()
253 		rgb->pll_d2_out0 = clk_get_sys(NULL, "pll_d2_out0");  in tegra_dc_rgb_probe()
254 		if (IS_ERR(rgb->pll_d2_out0)) {  in tegra_dc_rgb_probe()
255 			err = PTR_ERR(rgb->pll_d2_out0);  in tegra_dc_rgb_probe()
256 			dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err);  in tegra_dc_rgb_probe()
261 	dc->rgb = &rgb->output;  in tegra_dc_rgb_probe()
266 	clk_put(rgb->pll_d_out0);  in tegra_dc_rgb_probe()
268 	tegra_output_remove(&rgb->output);  in tegra_dc_rgb_probe()
276 	if (!dc->rgb)  in tegra_dc_rgb_remove()
279 	rgb = to_rgb(dc->rgb);  in tegra_dc_rgb_remove()
280 	clk_put(rgb->pll_d2_out0);  in tegra_dc_rgb_remove()
281 	clk_put(rgb->pll_d_out0);  in tegra_dc_rgb_remove()
283 	tegra_output_remove(dc->rgb);  in tegra_dc_rgb_remove()
284 	dc->rgb = NULL;  in tegra_dc_rgb_remove()
289 	struct tegra_output *output = dc->rgb;  in tegra_dc_rgb_init()
293 	if (!dc->rgb)  in tegra_dc_rgb_init()
294 		return -ENODEV;  in tegra_dc_rgb_init()
296 	drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);  in tegra_dc_rgb_init()
297 	drm_encoder_helper_add(&output->encoder,  in tegra_dc_rgb_init()
301 	 * Wrap directly-connected panel into DRM bridge in order to let  in tegra_dc_rgb_init()
304 	if (output->panel) {  in tegra_dc_rgb_init()
305 		output->bridge = devm_drm_panel_bridge_add(output->dev,  in tegra_dc_rgb_init()
306 							   output->panel);  in tegra_dc_rgb_init()
307 		if (IS_ERR(output->bridge)) {  in tegra_dc_rgb_init()
308 			dev_err(output->dev,  in tegra_dc_rgb_init()
310 				output->bridge);  in tegra_dc_rgb_init()
311 			return PTR_ERR(output->bridge);  in tegra_dc_rgb_init()
314 		output->panel = NULL;  in tegra_dc_rgb_init()
318 	 * Tegra devices that have LVDS panel utilize LVDS encoder bridge  in tegra_dc_rgb_init()
319 	 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that  in tegra_dc_rgb_init()
322 	 * Encoder usually have a power-down control which needs to be enabled  in tegra_dc_rgb_init()
324 	 * use an older device-tree version didn't model the bridge, assuming  in tegra_dc_rgb_init()
325 	 * that encoder is turned ON by default, while today's DRM allows us  in tegra_dc_rgb_init()
326 	 * to model LVDS encoder properly.  in tegra_dc_rgb_init()
328 	 * Newer device-trees utilize LVDS encoder bridge, which provides  in tegra_dc_rgb_init()
331 	 * For older device-trees we wrapped panel into the panel-bridge.  in tegra_dc_rgb_init()
333 	if (output->bridge) {  in tegra_dc_rgb_init()
334 		err = drm_bridge_attach(&output->encoder, output->bridge,  in tegra_dc_rgb_init()
339 		connector = drm_bridge_connector_init(drm, &output->encoder);  in tegra_dc_rgb_init()
341 			dev_err(output->dev,  in tegra_dc_rgb_init()
347 		drm_connector_attach_encoder(connector, &output->encoder);  in tegra_dc_rgb_init()
352 		dev_err(output->dev, "failed to initialize output: %d\n", err);  in tegra_dc_rgb_init()
361 	output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);  in tegra_dc_rgb_init()
368 	if (dc->rgb)  in tegra_dc_rgb_exit()
369 		tegra_output_exit(dc->rgb);  in tegra_dc_rgb_exit()