Lines Matching refs:tegra_plane_writel
107 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
361 tegra_plane_writel(plane, value,
382 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_LINEBUF_CONFIG);
386 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_FETCH_METER);
391 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA);
395 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB);
400 tegra_plane_writel(plane, value, DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER);
405 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG);
411 tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
515 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
568 tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
574 tegra_plane_writel(p, value, DC_WIN_BLEND_MATCH_SELECT);
579 tegra_plane_writel(p, value, DC_WIN_BLEND_NOMATCH_SELECT);
582 tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
601 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
608 tegra_plane_writel(p, incr, DC_WIN_SET_INPUT_SCALER_HPHASE_INCR);
609 tegra_plane_writel(p, init, DC_WIN_SET_INPUT_SCALER_H_START_PHASE);
619 tegra_plane_writel(p, incr, DC_WIN_SET_INPUT_SCALER_VPHASE_INCR);
620 tegra_plane_writel(p, init, DC_WIN_SET_INPUT_SCALER_V_START_PHASE);
625 tegra_plane_writel(p, bypass, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
628 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
643 tegra_plane_writel(p, tegra_plane_state->format, DC_WIN_COLOR_DEPTH);
644 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
648 tegra_plane_writel(p, value, DC_WIN_POSITION);
651 tegra_plane_writel(p, value, DC_WIN_SIZE);
654 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
657 tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
659 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
660 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR);
663 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
669 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U);
670 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U);
676 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);
677 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);
685 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);
687 tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U);
688 tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_HI_U);
689 tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_V);
690 tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_HI_V);
691 tegra_plane_writel(p, 0, DC_WIN_PLANAR_STORAGE_UV);
709 tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
713 tegra_plane_writel(p, value, DC_WINBUF_CROPPED_POINT);
736 tegra_plane_writel(p, value, DC_WINBUF_SURFACE_KIND);
742 tegra_plane_writel(p, value, DC_WIN_WINDOW_SET_CONTROL);