Lines Matching +full:sot +full:- +full:5 +full:x3
1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
119 trace_dsi_writel(dsi->dev, offset, value); in tegra_dsi_writel()
120 writel(value, dsi->regs + (offset << 2)); in tegra_dsi_writel()
201 struct drm_info_node *node = s->private; in tegra_dsi_show_regs()
202 struct tegra_dsi *dsi = node->info_ent->data; in tegra_dsi_show_regs()
203 struct drm_crtc *crtc = dsi->output.encoder.crtc; in tegra_dsi_show_regs()
204 struct drm_device *drm = node->minor->dev; in tegra_dsi_show_regs()
210 if (!crtc || !crtc->state->active) { in tegra_dsi_show_regs()
211 err = -EBUSY; in tegra_dsi_show_regs()
218 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, in tegra_dsi_show_regs()
235 struct drm_minor *minor = connector->dev->primary; in tegra_dsi_late_register()
236 struct dentry *root = connector->debugfs_entry; in tegra_dsi_late_register()
239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dsi_late_register()
241 if (!dsi->debugfs_files) in tegra_dsi_late_register()
242 return -ENOMEM; in tegra_dsi_late_register()
245 dsi->debugfs_files[i].data = dsi; in tegra_dsi_late_register()
247 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); in tegra_dsi_late_register()
258 drm_debugfs_remove_files(dsi->debugfs_files, count, in tegra_dsi_early_unregister()
259 connector->debugfs_entry, in tegra_dsi_early_unregister()
260 connector->dev->primary); in tegra_dsi_early_unregister()
261 kfree(dsi->debugfs_files); in tegra_dsi_early_unregister()
262 dsi->debugfs_files = NULL; in tegra_dsi_early_unregister()
276 * non-burst mode with sync pulses
293 [ 5] = 0,
314 * non-burst mode with sync events
328 [ 5] = 0,
349 [ 5] = 0,
354 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
364 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | in tegra_dsi_set_phy_timing()
365 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | in tegra_dsi_set_phy_timing()
366 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | in tegra_dsi_set_phy_timing()
367 DSI_TIMING_FIELD(timing->hsprepare, period, 1); in tegra_dsi_set_phy_timing()
370 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | in tegra_dsi_set_phy_timing()
371 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | in tegra_dsi_set_phy_timing()
372 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | in tegra_dsi_set_phy_timing()
373 DSI_TIMING_FIELD(timing->lpx, period, 1); in tegra_dsi_set_phy_timing()
376 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | in tegra_dsi_set_phy_timing()
377 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | in tegra_dsi_set_phy_timing()
381 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | in tegra_dsi_set_phy_timing()
382 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | in tegra_dsi_set_phy_timing()
383 DSI_TIMING_FIELD(timing->tago, period, 1); in tegra_dsi_set_phy_timing()
386 if (dsi->slave) in tegra_dsi_set_phy_timing()
387 tegra_dsi_set_phy_timing(dsi->slave, period, timing); in tegra_dsi_set_phy_timing()
411 return -EINVAL; in tegra_dsi_get_muldiv()
438 return -EINVAL; in tegra_dsi_get_format()
464 if (dsi->slave) in tegra_dsi_enable()
465 tegra_dsi_enable(dsi->slave); in tegra_dsi_enable()
470 if (dsi->master) in tegra_dsi_get_lanes()
471 return dsi->master->lanes + dsi->lanes; in tegra_dsi_get_lanes()
473 if (dsi->slave) in tegra_dsi_get_lanes()
474 return dsi->lanes + dsi->slave->lanes; in tegra_dsi_get_lanes()
476 return dsi->lanes; in tegra_dsi_get_lanes()
488 if (dsi->master) in tegra_dsi_configure()
489 state = tegra_dsi_get_state(dsi->master); in tegra_dsi_configure()
493 mul = state->mul; in tegra_dsi_configure()
494 div = state->div; in tegra_dsi_configure()
496 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { in tegra_dsi_configure()
497 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); in tegra_dsi_configure()
499 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { in tegra_dsi_configure()
500 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); in tegra_dsi_configure()
508 DSI_CONTROL_FORMAT(state->format) | in tegra_dsi_configure()
509 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_dsi_configure()
513 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); in tegra_dsi_configure()
520 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) in tegra_dsi_configure()
526 if (dsi->flags & MIPI_DSI_MODE_VIDEO) in tegra_dsi_configure()
538 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { in tegra_dsi_configure()
540 hact = mode->hdisplay * mul / div; in tegra_dsi_configure()
543 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; in tegra_dsi_configure()
546 hbp = (mode->htotal - mode->hsync_end) * mul / div; in tegra_dsi_configure()
548 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) in tegra_dsi_configure()
552 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; in tegra_dsi_configure()
555 hsw -= 10; in tegra_dsi_configure()
556 hbp -= 14; in tegra_dsi_configure()
557 hfp -= 8; in tegra_dsi_configure()
564 /* set SOL delay (for non-burst mode only) */ in tegra_dsi_configure()
571 if (dsi->master || dsi->slave) { in tegra_dsi_configure()
573 * For ganged mode, assume symmetric left-right mode. in tegra_dsi_configure()
575 bytes = 1 + (mode->hdisplay / 2) * mul / div; in tegra_dsi_configure()
578 bytes = 1 + mode->hdisplay * mul / div; in tegra_dsi_configure()
591 if (dsi->master || dsi->slave) { in tegra_dsi_configure()
593 unsigned int lanes = state->lanes; in tegra_dsi_configure()
601 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
603 value = bclk - bclk_ganged + delay + 20; in tegra_dsi_configure()
605 /* TODO: revisit for non-ganged mode */ in tegra_dsi_configure()
612 if (dsi->slave) { in tegra_dsi_configure()
613 tegra_dsi_configure(dsi->slave, pipe, mode); in tegra_dsi_configure()
616 * TODO: Support modes other than symmetrical left-right in tegra_dsi_configure()
619 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); in tegra_dsi_configure()
620 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, in tegra_dsi_configure()
621 mode->hdisplay / 2); in tegra_dsi_configure()
639 return -ETIMEDOUT; in tegra_dsi_wait_idle()
650 if (dsi->slave) in tegra_dsi_video_disable()
651 tegra_dsi_video_disable(dsi->slave); in tegra_dsi_video_disable()
694 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | in tegra_dsi_pad_calibrate()
695 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); in tegra_dsi_pad_calibrate()
698 err = tegra_mipi_start_calibration(dsi->mipi); in tegra_dsi_pad_calibrate()
702 return tegra_mipi_finish_calibration(dsi->mipi); in tegra_dsi_pad_calibrate()
711 /* one frame high-speed transmission timeout */ in tegra_dsi_set_timeout()
724 if (dsi->slave) in tegra_dsi_set_timeout()
725 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); in tegra_dsi_set_timeout()
732 if (dsi->slave) { in tegra_dsi_disable()
733 tegra_dsi_ganged_disable(dsi->slave); in tegra_dsi_disable()
741 if (dsi->slave) in tegra_dsi_disable()
742 tegra_dsi_disable(dsi->slave); in tegra_dsi_disable()
767 if (dsi->slave) in tegra_dsi_soft_reset()
768 tegra_dsi_soft_reset(dsi->slave); in tegra_dsi_soft_reset()
778 if (connector->state) { in tegra_dsi_connector_reset()
779 __drm_atomic_helper_connector_destroy_state(connector->state); in tegra_dsi_connector_reset()
780 kfree(connector->state); in tegra_dsi_connector_reset()
783 __drm_atomic_helper_connector_reset(connector, &state->base); in tegra_dsi_connector_reset()
789 struct tegra_dsi_state *state = to_dsi_state(connector->state); in tegra_dsi_connector_duplicate_state()
797 ©->base); in tegra_dsi_connector_duplicate_state()
799 return ©->base; in tegra_dsi_connector_duplicate_state()
829 if (dsi->slave) in tegra_dsi_unprepare()
830 tegra_dsi_unprepare(dsi->slave); in tegra_dsi_unprepare()
832 err = tegra_mipi_disable(dsi->mipi); in tegra_dsi_unprepare()
834 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", in tegra_dsi_unprepare()
837 err = host1x_client_suspend(&dsi->client); in tegra_dsi_unprepare()
839 dev_err(dsi->dev, "failed to suspend: %d\n", err); in tegra_dsi_unprepare()
845 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_dsi_encoder_disable()
850 if (output->panel) in tegra_dsi_encoder_disable()
851 drm_panel_disable(output->panel); in tegra_dsi_encoder_disable()
869 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); in tegra_dsi_encoder_disable()
873 if (output->panel) in tegra_dsi_encoder_disable()
874 drm_panel_unprepare(output->panel); in tegra_dsi_encoder_disable()
885 err = host1x_client_resume(&dsi->client); in tegra_dsi_prepare()
887 dev_err(dsi->dev, "failed to resume: %d\n", err); in tegra_dsi_prepare()
891 err = tegra_mipi_enable(dsi->mipi); in tegra_dsi_prepare()
893 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", in tegra_dsi_prepare()
898 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); in tegra_dsi_prepare()
900 if (dsi->slave) in tegra_dsi_prepare()
901 tegra_dsi_prepare(dsi->slave); in tegra_dsi_prepare()
908 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; in tegra_dsi_encoder_enable()
910 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_dsi_encoder_enable()
927 dev_err(dsi->dev, "failed to prepare: %d\n", err); in tegra_dsi_encoder_enable()
933 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); in tegra_dsi_encoder_enable()
936 * The D-PHY timing fields are expressed in byte-clock cycles, so in tegra_dsi_encoder_enable()
939 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); in tegra_dsi_encoder_enable()
941 if (output->panel) in tegra_dsi_encoder_enable()
942 drm_panel_prepare(output->panel); in tegra_dsi_encoder_enable()
944 tegra_dsi_configure(dsi, dc->pipe, mode); in tegra_dsi_encoder_enable()
956 if (output->panel) in tegra_dsi_encoder_enable()
957 drm_panel_enable(output->panel); in tegra_dsi_encoder_enable()
967 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_dsi_encoder_atomic_check()
973 state->pclk = crtc_state->mode.clock * 1000; in tegra_dsi_encoder_atomic_check()
975 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); in tegra_dsi_encoder_atomic_check()
979 state->lanes = tegra_dsi_get_lanes(dsi); in tegra_dsi_encoder_atomic_check()
981 err = tegra_dsi_get_format(dsi->format, &state->format); in tegra_dsi_encoder_atomic_check()
985 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); in tegra_dsi_encoder_atomic_check()
988 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); in tegra_dsi_encoder_atomic_check()
990 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, in tegra_dsi_encoder_atomic_check()
991 state->lanes); in tegra_dsi_encoder_atomic_check()
992 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, in tegra_dsi_encoder_atomic_check()
993 state->vrefresh); in tegra_dsi_encoder_atomic_check()
994 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); in tegra_dsi_encoder_atomic_check()
999 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; in tegra_dsi_encoder_atomic_check()
1000 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); in tegra_dsi_encoder_atomic_check()
1002 err = mipi_dphy_timing_get_default(&state->timing, state->period); in tegra_dsi_encoder_atomic_check()
1006 err = mipi_dphy_timing_validate(&state->timing, state->period); in tegra_dsi_encoder_atomic_check()
1008 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); in tegra_dsi_encoder_atomic_check()
1029 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; in tegra_dsi_encoder_atomic_check()
1031 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, in tegra_dsi_encoder_atomic_check()
1034 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_dsi_encoder_atomic_check()
1049 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dsi_init()
1054 if (!dsi->master) { in tegra_dsi_init()
1055 dsi->output.dev = client->dev; in tegra_dsi_init()
1057 drm_connector_init(drm, &dsi->output.connector, in tegra_dsi_init()
1060 drm_connector_helper_add(&dsi->output.connector, in tegra_dsi_init()
1062 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_dsi_init()
1064 drm_simple_encoder_init(drm, &dsi->output.encoder, in tegra_dsi_init()
1066 drm_encoder_helper_add(&dsi->output.encoder, in tegra_dsi_init()
1069 drm_connector_attach_encoder(&dsi->output.connector, in tegra_dsi_init()
1070 &dsi->output.encoder); in tegra_dsi_init()
1071 drm_connector_register(&dsi->output.connector); in tegra_dsi_init()
1073 err = tegra_output_init(drm, &dsi->output); in tegra_dsi_init()
1075 dev_err(dsi->dev, "failed to initialize output: %d\n", in tegra_dsi_init()
1078 dsi->output.encoder.possible_crtcs = 0x3; in tegra_dsi_init()
1088 tegra_output_exit(&dsi->output); in tegra_dsi_exit()
1096 struct device *dev = client->dev; in tegra_dsi_runtime_suspend()
1099 if (dsi->rst) { in tegra_dsi_runtime_suspend()
1100 err = reset_control_assert(dsi->rst); in tegra_dsi_runtime_suspend()
1109 clk_disable_unprepare(dsi->clk_lp); in tegra_dsi_runtime_suspend()
1110 clk_disable_unprepare(dsi->clk); in tegra_dsi_runtime_suspend()
1112 regulator_disable(dsi->vdd); in tegra_dsi_runtime_suspend()
1121 struct device *dev = client->dev; in tegra_dsi_runtime_resume()
1130 err = regulator_enable(dsi->vdd); in tegra_dsi_runtime_resume()
1136 err = clk_prepare_enable(dsi->clk); in tegra_dsi_runtime_resume()
1142 err = clk_prepare_enable(dsi->clk_lp); in tegra_dsi_runtime_resume()
1144 dev_err(dev, "cannot enable low-power clock: %d\n", err); in tegra_dsi_runtime_resume()
1150 if (dsi->rst) { in tegra_dsi_runtime_resume()
1151 err = reset_control_deassert(dsi->rst); in tegra_dsi_runtime_resume()
1161 clk_disable_unprepare(dsi->clk_lp); in tegra_dsi_runtime_resume()
1163 clk_disable_unprepare(dsi->clk); in tegra_dsi_runtime_resume()
1165 regulator_disable(dsi->vdd); in tegra_dsi_runtime_resume()
1183 parent = clk_get_parent(dsi->clk); in tegra_dsi_setup_clocks()
1185 return -EINVAL; in tegra_dsi_setup_clocks()
1187 err = clk_set_parent(parent, dsi->clk_parent); in tegra_dsi_setup_clocks()
1195 "SoT Error",
1196 "SoT Sync Error",
1199 "Low-Power Transmit Sync Error",
1203 "ECC Error, single-bit",
1204 "ECC Error, multi-bit",
1217 u8 *rx = msg->rx_buf; in tegra_dsi_read_response()
1229 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", in tegra_dsi_read_response()
1233 dev_dbg(dsi->dev, " %2u: %s\n", i, in tegra_dsi_read_response()
1257 dev_err(dsi->dev, "unhandled response type: %02x\n", in tegra_dsi_read_response()
1259 return -EPROTO; in tegra_dsi_read_response()
1262 size = min(size, msg->rx_len); in tegra_dsi_read_response()
1264 if (msg->rx_buf && size > 0) { in tegra_dsi_read_response()
1265 for (i = 0, j = 0; i < count - 1; i++, j += 4) { in tegra_dsi_read_response()
1266 u8 *rx = msg->rx_buf + j; in tegra_dsi_read_response()
1270 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) in tegra_dsi_read_response()
1293 return -ETIMEDOUT; in tegra_dsi_transmit()
1312 return -ETIMEDOUT; in tegra_dsi_wait_for_response()
1349 if (packet.size > dsi->video_fifo_depth * 4) in tegra_dsi_host_transfer()
1350 return -ENOSPC; in tegra_dsi_host_transfer()
1369 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) in tegra_dsi_host_transfer()
1376 if (packet.size > dsi->host_fifo_depth * 4) in tegra_dsi_host_transfer()
1385 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || in tegra_dsi_host_transfer()
1386 (msg->rx_buf && msg->rx_len > 0)) { in tegra_dsi_host_transfer()
1408 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || in tegra_dsi_host_transfer()
1409 (msg->rx_buf && msg->rx_len > 0)) { in tegra_dsi_host_transfer()
1420 dev_dbg(dsi->dev, "ACK\n"); in tegra_dsi_host_transfer()
1426 dev_dbg(dsi->dev, "ESCAPE\n"); in tegra_dsi_host_transfer()
1431 dev_err(dsi->dev, "unknown status: %08x\n", value); in tegra_dsi_host_transfer()
1438 dev_err(dsi->dev, in tegra_dsi_host_transfer()
1451 * For write commands, we have transmitted the 4-byte header in tegra_dsi_host_transfer()
1452 * plus the variable-length payload. in tegra_dsi_host_transfer()
1466 parent = clk_get_parent(dsi->slave->clk); in tegra_dsi_ganged_setup()
1468 return -EINVAL; in tegra_dsi_ganged_setup()
1470 err = clk_set_parent(parent, dsi->clk_parent); in tegra_dsi_ganged_setup()
1482 dsi->flags = device->mode_flags; in tegra_dsi_host_attach()
1483 dsi->format = device->format; in tegra_dsi_host_attach()
1484 dsi->lanes = device->lanes; in tegra_dsi_host_attach()
1486 if (dsi->slave) { in tegra_dsi_host_attach()
1489 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", in tegra_dsi_host_attach()
1490 dev_name(&device->dev)); in tegra_dsi_host_attach()
1494 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", in tegra_dsi_host_attach()
1504 if (!dsi->master) { in tegra_dsi_host_attach()
1505 struct tegra_output *output = &dsi->output; in tegra_dsi_host_attach()
1507 output->panel = of_drm_find_panel(device->dev.of_node); in tegra_dsi_host_attach()
1508 if (IS_ERR(output->panel)) in tegra_dsi_host_attach()
1509 output->panel = NULL; in tegra_dsi_host_attach()
1511 if (output->panel && output->connector.dev) in tegra_dsi_host_attach()
1512 drm_helper_hpd_irq_event(output->connector.dev); in tegra_dsi_host_attach()
1522 struct tegra_output *output = &dsi->output; in tegra_dsi_host_detach()
1524 if (output->panel && &device->dev == output->panel->dev) { in tegra_dsi_host_detach()
1525 output->panel = NULL; in tegra_dsi_host_detach()
1527 if (output->connector.dev) in tegra_dsi_host_detach()
1528 drm_helper_hpd_irq_event(output->connector.dev); in tegra_dsi_host_detach()
1544 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); in tegra_dsi_ganged_probe()
1549 return -EPROBE_DEFER; in tegra_dsi_ganged_probe()
1551 dsi->slave = platform_get_drvdata(gangster); in tegra_dsi_ganged_probe()
1553 if (!dsi->slave) { in tegra_dsi_ganged_probe()
1554 put_device(&gangster->dev); in tegra_dsi_ganged_probe()
1555 return -EPROBE_DEFER; in tegra_dsi_ganged_probe()
1558 dsi->slave->master = dsi; in tegra_dsi_ganged_probe()
1570 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); in tegra_dsi_probe()
1572 return -ENOMEM; in tegra_dsi_probe()
1574 dsi->output.dev = dsi->dev = &pdev->dev; in tegra_dsi_probe()
1575 dsi->video_fifo_depth = 1920; in tegra_dsi_probe()
1576 dsi->host_fifo_depth = 64; in tegra_dsi_probe()
1582 err = tegra_output_probe(&dsi->output); in tegra_dsi_probe()
1586 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; in tegra_dsi_probe()
1593 dsi->flags = MIPI_DSI_MODE_VIDEO; in tegra_dsi_probe()
1594 dsi->format = MIPI_DSI_FMT_RGB888; in tegra_dsi_probe()
1595 dsi->lanes = 4; in tegra_dsi_probe()
1597 if (!pdev->dev.pm_domain) { in tegra_dsi_probe()
1598 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); in tegra_dsi_probe()
1599 if (IS_ERR(dsi->rst)) { in tegra_dsi_probe()
1600 err = PTR_ERR(dsi->rst); in tegra_dsi_probe()
1605 dsi->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dsi_probe()
1606 if (IS_ERR(dsi->clk)) { in tegra_dsi_probe()
1607 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk), in tegra_dsi_probe()
1612 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); in tegra_dsi_probe()
1613 if (IS_ERR(dsi->clk_lp)) { in tegra_dsi_probe()
1614 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), in tegra_dsi_probe()
1615 "cannot get low-power clock\n"); in tegra_dsi_probe()
1619 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_dsi_probe()
1620 if (IS_ERR(dsi->clk_parent)) { in tegra_dsi_probe()
1621 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent), in tegra_dsi_probe()
1626 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); in tegra_dsi_probe()
1627 if (IS_ERR(dsi->vdd)) { in tegra_dsi_probe()
1628 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd), in tegra_dsi_probe()
1635 dev_err(&pdev->dev, "cannot setup clocks\n"); in tegra_dsi_probe()
1640 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dsi_probe()
1641 if (IS_ERR(dsi->regs)) { in tegra_dsi_probe()
1642 err = PTR_ERR(dsi->regs); in tegra_dsi_probe()
1646 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); in tegra_dsi_probe()
1647 if (IS_ERR(dsi->mipi)) { in tegra_dsi_probe()
1648 err = PTR_ERR(dsi->mipi); in tegra_dsi_probe()
1652 dsi->host.ops = &tegra_dsi_host_ops; in tegra_dsi_probe()
1653 dsi->host.dev = &pdev->dev; in tegra_dsi_probe()
1655 err = mipi_dsi_host_register(&dsi->host); in tegra_dsi_probe()
1657 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); in tegra_dsi_probe()
1662 pm_runtime_enable(&pdev->dev); in tegra_dsi_probe()
1664 INIT_LIST_HEAD(&dsi->client.list); in tegra_dsi_probe()
1665 dsi->client.ops = &dsi_client_ops; in tegra_dsi_probe()
1666 dsi->client.dev = &pdev->dev; in tegra_dsi_probe()
1668 err = host1x_client_register(&dsi->client); in tegra_dsi_probe()
1670 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_dsi_probe()
1678 pm_runtime_disable(&pdev->dev); in tegra_dsi_probe()
1679 mipi_dsi_host_unregister(&dsi->host); in tegra_dsi_probe()
1681 tegra_mipi_free(dsi->mipi); in tegra_dsi_probe()
1683 tegra_output_remove(&dsi->output); in tegra_dsi_probe()
1691 pm_runtime_disable(&pdev->dev); in tegra_dsi_remove()
1693 host1x_client_unregister(&dsi->client); in tegra_dsi_remove()
1695 tegra_output_remove(&dsi->output); in tegra_dsi_remove()
1697 mipi_dsi_host_unregister(&dsi->host); in tegra_dsi_remove()
1698 tegra_mipi_free(dsi->mipi); in tegra_dsi_remove()
1702 { .compatible = "nvidia,tegra210-dsi", },
1703 { .compatible = "nvidia,tegra132-dsi", },
1704 { .compatible = "nvidia,tegra124-dsi", },
1705 { .compatible = "nvidia,tegra114-dsi", },
1712 .name = "tegra-dsi",