Lines Matching +full:tegra20 +full:- +full:gr3d
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
27 #include <asm/dma-iommu.h>
76 struct drm_device *drm = old_state->dev;
77 struct tegra_drm *tegra = drm->dev_private;
79 if (tegra->hub) {
108 return -ENOMEM;
110 idr_init_base(&fpriv->legacy_contexts, 1);
111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
112 xa_init(&fpriv->syncpoints);
113 mutex_init(&fpriv->lock);
114 filp->driver_priv = fpriv;
121 context->client->ops->close_channel(context);
122 pm_runtime_put(context->client->base.dev);
134 err = get_user(cmdbuf, &src->cmdbuf.handle);
138 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
142 err = get_user(target, &src->target.handle);
146 err = get_user(dest->target.offset, &src->target.offset);
150 err = get_user(dest->shift, &src->shift);
154 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
156 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
157 if (!dest->cmdbuf.bo)
158 return -ENOENT;
160 dest->target.bo = tegra_gem_lookup(file, target);
161 if (!dest->target.bo)
162 return -ENOENT;
171 struct host1x_client *client = &context->client->base;
172 unsigned int num_cmdbufs = args->num_cmdbufs;
173 unsigned int num_relocs = args->num_relocs;
178 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
185 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
186 user_relocs = u64_to_user_ptr(args->relocs);
187 user_syncpt = u64_to_user_ptr(args->syncpts);
190 if (args->num_syncpts != 1)
191 return -EINVAL;
194 if (args->num_waitchks != 0)
195 return -EINVAL;
197 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
198 args->num_relocs, false);
200 return -ENOMEM;
202 job->num_relocs = args->num_relocs;
203 job->client = client;
204 job->class = client->class;
205 job->serialize = true;
206 job->syncpt_recovery = true;
216 err = -ENOMEM;
230 err = -EFAULT;
239 err = -EINVAL;
245 err = -ENOENT;
251 refs[num_refs++] = &obj->gem;
254 * Gather buffer base address must be 4-bytes aligned,
258 if (offset & 3 || offset > obj->gem.size) {
259 err = -EINVAL;
264 num_cmdbufs--;
269 while (num_relocs--) {
273 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
279 reloc = &job->relocs[num_relocs];
280 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
281 refs[num_refs++] = &obj->gem;
288 if (reloc->cmdbuf.offset & 3 ||
289 reloc->cmdbuf.offset >= obj->gem.size) {
290 err = -EINVAL;
294 obj = host1x_to_tegra_bo(reloc->target.bo);
295 refs[num_refs++] = &obj->gem;
297 if (reloc->target.offset >= obj->gem.size) {
298 err = -EINVAL;
304 err = -EFAULT;
311 err = -ENOENT;
315 job->is_addr_reg = context->client->ops->is_addr_reg;
316 job->is_valid_class = context->client->ops->is_valid_class;
317 job->syncpt_incrs = syncpt.incrs;
318 job->syncpt = sp;
319 job->timeout = 10000;
321 if (args->timeout && args->timeout < 10000)
322 job->timeout = args->timeout;
324 err = host1x_job_pin(job, context->client->base.dev);
334 args->fence = job->syncpt_end;
337 while (num_refs--)
355 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
356 &args->handle);
370 gem = drm_gem_object_lookup(file, args->handle);
372 return -EINVAL;
376 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
386 struct host1x *host = dev_get_drvdata(drm->dev->parent);
390 sp = host1x_syncpt_get_by_id_noref(host, args->id);
392 return -EINVAL;
394 args->value = host1x_syncpt_read_min(sp);
401 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
405 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
407 return -EINVAL;
415 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
419 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
421 return -EINVAL;
423 return host1x_syncpt_wait(sp, args->thresh,
424 msecs_to_jiffies(args->timeout),
425 &args->value);
434 err = pm_runtime_resume_and_get(client->base.dev);
438 err = client->ops->open_channel(client, context);
440 pm_runtime_put(client->base.dev);
444 err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
446 client->ops->close_channel(context);
447 pm_runtime_put(client->base.dev);
451 context->client = client;
452 context->id = err;
460 struct tegra_drm_file *fpriv = file->driver_priv;
461 struct tegra_drm *tegra = drm->dev_private;
465 int err = -ENODEV;
469 return -ENOMEM;
471 mutex_lock(&fpriv->lock);
473 list_for_each_entry(client, &tegra->clients, list)
474 if (client->base.class == args->client) {
479 args->context = context->id;
486 mutex_unlock(&fpriv->lock);
493 struct tegra_drm_file *fpriv = file->driver_priv;
498 mutex_lock(&fpriv->lock);
500 context = idr_find(&fpriv->legacy_contexts, args->context);
502 err = -EINVAL;
506 idr_remove(&fpriv->legacy_contexts, context->id);
510 mutex_unlock(&fpriv->lock);
517 struct tegra_drm_file *fpriv = file->driver_priv;
523 mutex_lock(&fpriv->lock);
525 context = idr_find(&fpriv->legacy_contexts, args->context);
527 err = -ENODEV;
531 if (args->index >= context->client->base.num_syncpts) {
532 err = -EINVAL;
536 syncpt = context->client->base.syncpts[args->index];
537 args->id = host1x_syncpt_id(syncpt);
540 mutex_unlock(&fpriv->lock);
547 struct tegra_drm_file *fpriv = file->driver_priv;
552 mutex_lock(&fpriv->lock);
554 context = idr_find(&fpriv->legacy_contexts, args->context);
556 err = -ENODEV;
560 err = context->client->ops->submit(context, args, drm, file);
563 mutex_unlock(&fpriv->lock);
570 struct tegra_drm_file *fpriv = file->driver_priv;
577 mutex_lock(&fpriv->lock);
579 context = idr_find(&fpriv->legacy_contexts, args->context);
581 err = -ENODEV;
585 if (args->syncpt >= context->client->base.num_syncpts) {
586 err = -EINVAL;
590 syncpt = context->client->base.syncpts[args->syncpt];
594 err = -ENXIO;
598 args->id = host1x_syncpt_base_id(base);
601 mutex_unlock(&fpriv->lock);
614 switch (args->mode) {
618 if (args->value != 0)
619 return -EINVAL;
626 if (args->value != 0)
627 return -EINVAL;
634 if (args->value > 5)
635 return -EINVAL;
637 value = args->value;
641 return -EINVAL;
644 gem = drm_gem_object_lookup(file, args->handle);
646 return -ENOENT;
650 bo->tiling.mode = mode;
651 bo->tiling.value = value;
666 gem = drm_gem_object_lookup(file, args->handle);
668 return -ENOENT;
672 switch (bo->tiling.mode) {
674 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
675 args->value = 0;
679 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
680 args->value = 0;
684 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
685 args->value = bo->tiling.value;
689 err = -EINVAL;
705 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
706 return -EINVAL;
708 gem = drm_gem_object_lookup(file, args->handle);
710 return -ENOENT;
713 bo->flags = 0;
715 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
716 bo->flags |= TEGRA_BO_BOTTOM_UP;
730 gem = drm_gem_object_lookup(file, args->handle);
732 return -ENOENT;
735 args->flags = 0;
737 if (bo->flags & TEGRA_BO_BOTTOM_UP)
738 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
818 struct tegra_drm_file *fpriv = file->driver_priv;
820 mutex_lock(&fpriv->lock);
821 idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
823 mutex_unlock(&fpriv->lock);
825 idr_destroy(&fpriv->legacy_contexts);
826 mutex_destroy(&fpriv->lock);
833 struct drm_info_node *node = (struct drm_info_node *)s->private;
834 struct drm_device *drm = node->minor->dev;
837 mutex_lock(&drm->mode_config.fb_lock);
839 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
841 fb->base.id, fb->width, fb->height,
842 fb->format->depth,
843 fb->format->cpp[0] * 8,
847 mutex_unlock(&drm->mode_config.fb_lock);
854 struct drm_info_node *node = (struct drm_info_node *)s->private;
855 struct drm_device *drm = node->minor->dev;
856 struct tegra_drm *tegra = drm->dev_private;
859 if (tegra->domain) {
860 mutex_lock(&tegra->mm_lock);
861 drm_mm_print(&tegra->mm, &p);
862 mutex_unlock(&tegra->mm_lock);
877 minor->debugfs_root, minor);
914 client->shared_channel = host1x_channel_request(&client->base);
915 if (!client->shared_channel)
916 return -EBUSY;
918 mutex_lock(&tegra->clients_lock);
919 list_add_tail(&client->list, &tegra->clients);
920 client->drm = tegra;
921 mutex_unlock(&tegra->clients_lock);
929 mutex_lock(&tegra->clients_lock);
930 list_del_init(&client->list);
931 client->drm = NULL;
932 mutex_unlock(&tegra->clients_lock);
934 if (client->shared_channel)
935 host1x_channel_put(client->shared_channel);
942 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
943 struct drm_device *drm = dev_get_drvdata(client->host);
944 struct tegra_drm *tegra = drm->dev_private;
949 if (client->dev->archdata.mapping) {
951 to_dma_iommu_mapping(client->dev);
952 arm_iommu_detach_device(client->dev);
955 domain = iommu_get_domain_for_dev(client->dev);
962 * domain. This allows using the IOMMU-backed DMA API.
964 if (domain && domain->type != IOMMU_DOMAIN_IDENTITY &&
965 domain != tegra->domain)
968 if (tegra->domain) {
969 group = iommu_group_get(client->dev);
971 return -ENODEV;
973 if (domain != tegra->domain) {
974 err = iommu_attach_group(tegra->domain, group);
981 tegra->use_explicit_iommu = true;
984 client->group = group;
991 struct drm_device *drm = dev_get_drvdata(client->host);
992 struct tegra_drm *tegra = drm->dev_private;
995 if (client->group) {
1001 domain = iommu_get_domain_for_dev(client->dev);
1003 iommu_detach_group(tegra->domain, client->group);
1005 iommu_group_put(client->group);
1006 client->group = NULL;
1017 if (tegra->domain)
1018 size = iova_align(&tegra->carveout.domain, size);
1023 if (!tegra->domain) {
1025 * Many units only support 32-bit addresses, even on 64-bit
1026 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1028 * lower 32-bit range.
1035 return ERR_PTR(-ENOMEM);
1037 if (!tegra->domain) {
1046 alloc = alloc_iova(&tegra->carveout.domain,
1047 size >> tegra->carveout.shift,
1048 tegra->carveout.limit, true);
1050 err = -EBUSY;
1054 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1055 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1063 __free_iova(&tegra->carveout.domain, alloc);
1073 if (tegra->domain)
1074 size = iova_align(&tegra->carveout.domain, size);
1078 if (tegra->domain) {
1079 iommu_unmap(tegra->domain, dma, size);
1080 free_iova(&tegra->carveout.domain,
1081 iova_pfn(&tegra->carveout.domain, dma));
1089 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1093 if (of_machine_is_compatible("nvidia,tegra20"))
1098 * likely to be allocated beyond the 32-bit boundary if sufficient
1103 * 32-bit boundary.
1123 domain = iommu_get_domain_for_dev(dev->dev.parent);
1126 * Tegra20 and Tegra30 don't support addressing memory beyond the
1127 * 32-bit boundary, so the regular GATHER opcodes will always be
1139 struct device *dma_dev = dev->dev.parent;
1144 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1150 err = -ENOMEM;
1155 tegra->domain = iommu_paging_domain_alloc(dma_dev);
1156 if (IS_ERR(tegra->domain)) {
1157 err = PTR_ERR(tegra->domain);
1166 mutex_init(&tegra->clients_lock);
1167 INIT_LIST_HEAD(&tegra->clients);
1169 dev_set_drvdata(&dev->dev, drm);
1170 drm->dev_private = tegra;
1171 tegra->drm = drm;
1175 drm->mode_config.min_width = 0;
1176 drm->mode_config.min_height = 0;
1177 drm->mode_config.max_width = 0;
1178 drm->mode_config.max_height = 0;
1180 drm->mode_config.normalize_zpos = true;
1182 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1183 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1196 tegra->hmask = drm->mode_config.max_width - 1;
1197 tegra->vmask = drm->mode_config.max_height - 1;
1199 if (tegra->use_explicit_iommu) {
1201 u64 dma_mask = dma_get_mask(&dev->dev);
1205 start = tegra->domain->geometry.aperture_start & dma_mask;
1206 end = tegra->domain->geometry.aperture_end & dma_mask;
1209 gem_end = end - CARVEOUT_SZ;
1213 order = __ffs(tegra->domain->pgsize_bitmap);
1214 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1217 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1218 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1220 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1221 mutex_init(&tegra->mm_lock);
1224 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1225 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1227 } else if (tegra->domain) {
1228 iommu_domain_free(tegra->domain);
1229 tegra->domain = NULL;
1233 if (tegra->hub) {
1234 err = tegra_display_hub_prepare(tegra->hub);
1239 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1240 drm->max_vblank_count = 0xffffffff;
1242 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1257 if (drm->mode_config.num_crtc > 0) {
1266 drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1278 if (tegra->hub)
1279 tegra_display_hub_cleanup(tegra->hub);
1281 if (tegra->domain) {
1282 mutex_destroy(&tegra->mm_lock);
1283 drm_mm_takedown(&tegra->mm);
1284 put_iova_domain(&tegra->carveout.domain);
1293 if (tegra->domain)
1294 iommu_domain_free(tegra->domain);
1304 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1305 struct tegra_drm *tegra = drm->dev_private;
1314 if (tegra->hub)
1315 tegra_display_hub_cleanup(tegra->hub);
1319 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1321 if (tegra->domain) {
1322 mutex_destroy(&tegra->mm_lock);
1323 drm_mm_takedown(&tegra->mm);
1324 put_iova_domain(&tegra->carveout.domain);
1326 iommu_domain_free(tegra->domain);
1337 drm_atomic_helper_shutdown(dev_get_drvdata(&dev->dev));
1360 { .compatible = "nvidia,tegra20-dc", },
1361 { .compatible = "nvidia,tegra20-hdmi", },
1362 { .compatible = "nvidia,tegra20-gr2d", },
1363 { .compatible = "nvidia,tegra20-gr3d", },
1364 { .compatible = "nvidia,tegra30-dc", },
1365 { .compatible = "nvidia,tegra30-hdmi", },
1366 { .compatible = "nvidia,tegra30-gr2d", },
1367 { .compatible = "nvidia,tegra30-gr3d", },
1368 { .compatible = "nvidia,tegra114-dc", },
1369 { .compatible = "nvidia,tegra114-dsi", },
1370 { .compatible = "nvidia,tegra114-hdmi", },
1371 { .compatible = "nvidia,tegra114-gr2d", },
1372 { .compatible = "nvidia,tegra114-gr3d", },
1373 { .compatible = "nvidia,tegra124-dc", },
1374 { .compatible = "nvidia,tegra124-sor", },
1375 { .compatible = "nvidia,tegra124-hdmi", },
1376 { .compatible = "nvidia,tegra124-dsi", },
1377 { .compatible = "nvidia,tegra124-vic", },
1378 { .compatible = "nvidia,tegra132-dsi", },
1379 { .compatible = "nvidia,tegra210-dc", },
1380 { .compatible = "nvidia,tegra210-dsi", },
1381 { .compatible = "nvidia,tegra210-sor", },
1382 { .compatible = "nvidia,tegra210-sor1", },
1383 { .compatible = "nvidia,tegra210-vic", },
1384 { .compatible = "nvidia,tegra210-nvdec", },
1385 { .compatible = "nvidia,tegra186-display", },
1386 { .compatible = "nvidia,tegra186-dc", },
1387 { .compatible = "nvidia,tegra186-sor", },
1388 { .compatible = "nvidia,tegra186-sor1", },
1389 { .compatible = "nvidia,tegra186-vic", },
1390 { .compatible = "nvidia,tegra186-nvdec", },
1391 { .compatible = "nvidia,tegra194-display", },
1392 { .compatible = "nvidia,tegra194-dc", },
1393 { .compatible = "nvidia,tegra194-sor", },
1394 { .compatible = "nvidia,tegra194-vic", },
1395 { .compatible = "nvidia,tegra194-nvdec", },
1396 { .compatible = "nvidia,tegra234-vic", },
1397 { .compatible = "nvidia,tegra234-nvdec", },
1430 return -ENODEV;
1455 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");