Lines Matching +full:display +full:- +full:hub
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
28 #include <asm/dma-iommu.h>
77 struct drm_device *drm = old_state->dev;
78 struct tegra_drm *tegra = drm->dev_private;
80 if (tegra->hub) {
109 return -ENOMEM;
111 idr_init_base(&fpriv->legacy_contexts, 1);
112 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
113 xa_init(&fpriv->syncpoints);
114 mutex_init(&fpriv->lock);
115 filp->driver_priv = fpriv;
122 context->client->ops->close_channel(context);
123 pm_runtime_put(context->client->base.dev);
135 err = get_user(cmdbuf, &src->cmdbuf.handle);
139 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
143 err = get_user(target, &src->target.handle);
147 err = get_user(dest->target.offset, &src->target.offset);
151 err = get_user(dest->shift, &src->shift);
155 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
157 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
158 if (!dest->cmdbuf.bo)
159 return -ENOENT;
161 dest->target.bo = tegra_gem_lookup(file, target);
162 if (!dest->target.bo)
163 return -ENOENT;
172 struct host1x_client *client = &context->client->base;
173 unsigned int num_cmdbufs = args->num_cmdbufs;
174 unsigned int num_relocs = args->num_relocs;
179 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
186 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
187 user_relocs = u64_to_user_ptr(args->relocs);
188 user_syncpt = u64_to_user_ptr(args->syncpts);
191 if (args->num_syncpts != 1)
192 return -EINVAL;
195 if (args->num_waitchks != 0)
196 return -EINVAL;
198 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
199 args->num_relocs, false);
201 return -ENOMEM;
203 job->num_relocs = args->num_relocs;
204 job->client = client;
205 job->class = client->class;
206 job->serialize = true;
207 job->syncpt_recovery = true;
217 err = -ENOMEM;
231 err = -EFAULT;
240 err = -EINVAL;
246 err = -ENOENT;
252 refs[num_refs++] = &obj->gem;
255 * Gather buffer base address must be 4-bytes aligned,
259 if (offset & 3 || offset > obj->gem.size) {
260 err = -EINVAL;
265 num_cmdbufs--;
270 while (num_relocs--) {
274 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
280 reloc = &job->relocs[num_relocs];
281 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
282 refs[num_refs++] = &obj->gem;
289 if (reloc->cmdbuf.offset & 3 ||
290 reloc->cmdbuf.offset >= obj->gem.size) {
291 err = -EINVAL;
295 obj = host1x_to_tegra_bo(reloc->target.bo);
296 refs[num_refs++] = &obj->gem;
298 if (reloc->target.offset >= obj->gem.size) {
299 err = -EINVAL;
305 err = -EFAULT;
312 err = -ENOENT;
316 job->is_addr_reg = context->client->ops->is_addr_reg;
317 job->is_valid_class = context->client->ops->is_valid_class;
318 job->syncpt_incrs = syncpt.incrs;
319 job->syncpt = sp;
320 job->timeout = 10000;
322 if (args->timeout && args->timeout < 10000)
323 job->timeout = args->timeout;
325 err = host1x_job_pin(job, context->client->base.dev);
335 args->fence = job->syncpt_end;
338 while (num_refs--)
356 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
357 &args->handle);
371 gem = drm_gem_object_lookup(file, args->handle);
373 return -EINVAL;
377 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
387 struct host1x *host = dev_get_drvdata(drm->dev->parent);
391 sp = host1x_syncpt_get_by_id_noref(host, args->id);
393 return -EINVAL;
395 args->value = host1x_syncpt_read_min(sp);
402 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
406 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
408 return -EINVAL;
416 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
420 sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
422 return -EINVAL;
424 return host1x_syncpt_wait(sp, args->thresh,
425 msecs_to_jiffies(args->timeout),
426 &args->value);
435 err = pm_runtime_resume_and_get(client->base.dev);
439 err = client->ops->open_channel(client, context);
441 pm_runtime_put(client->base.dev);
445 err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
447 client->ops->close_channel(context);
448 pm_runtime_put(client->base.dev);
452 context->client = client;
453 context->id = err;
461 struct tegra_drm_file *fpriv = file->driver_priv;
462 struct tegra_drm *tegra = drm->dev_private;
466 int err = -ENODEV;
470 return -ENOMEM;
472 mutex_lock(&fpriv->lock);
474 list_for_each_entry(client, &tegra->clients, list)
475 if (client->base.class == args->client) {
480 args->context = context->id;
487 mutex_unlock(&fpriv->lock);
494 struct tegra_drm_file *fpriv = file->driver_priv;
499 mutex_lock(&fpriv->lock);
501 context = idr_find(&fpriv->legacy_contexts, args->context);
503 err = -EINVAL;
507 idr_remove(&fpriv->legacy_contexts, context->id);
511 mutex_unlock(&fpriv->lock);
518 struct tegra_drm_file *fpriv = file->driver_priv;
524 mutex_lock(&fpriv->lock);
526 context = idr_find(&fpriv->legacy_contexts, args->context);
528 err = -ENODEV;
532 if (args->index >= context->client->base.num_syncpts) {
533 err = -EINVAL;
537 syncpt = context->client->base.syncpts[args->index];
538 args->id = host1x_syncpt_id(syncpt);
541 mutex_unlock(&fpriv->lock);
548 struct tegra_drm_file *fpriv = file->driver_priv;
553 mutex_lock(&fpriv->lock);
555 context = idr_find(&fpriv->legacy_contexts, args->context);
557 err = -ENODEV;
561 err = context->client->ops->submit(context, args, drm, file);
564 mutex_unlock(&fpriv->lock);
571 struct tegra_drm_file *fpriv = file->driver_priv;
578 mutex_lock(&fpriv->lock);
580 context = idr_find(&fpriv->legacy_contexts, args->context);
582 err = -ENODEV;
586 if (args->syncpt >= context->client->base.num_syncpts) {
587 err = -EINVAL;
591 syncpt = context->client->base.syncpts[args->syncpt];
595 err = -ENXIO;
599 args->id = host1x_syncpt_base_id(base);
602 mutex_unlock(&fpriv->lock);
615 switch (args->mode) {
619 if (args->value != 0)
620 return -EINVAL;
627 if (args->value != 0)
628 return -EINVAL;
635 if (args->value > 5)
636 return -EINVAL;
638 value = args->value;
642 return -EINVAL;
645 gem = drm_gem_object_lookup(file, args->handle);
647 return -ENOENT;
651 bo->tiling.mode = mode;
652 bo->tiling.value = value;
667 gem = drm_gem_object_lookup(file, args->handle);
669 return -ENOENT;
673 switch (bo->tiling.mode) {
675 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
676 args->value = 0;
680 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
681 args->value = 0;
685 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
686 args->value = bo->tiling.value;
690 err = -EINVAL;
706 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
707 return -EINVAL;
709 gem = drm_gem_object_lookup(file, args->handle);
711 return -ENOENT;
714 bo->flags = 0;
716 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
717 bo->flags |= TEGRA_BO_BOTTOM_UP;
731 gem = drm_gem_object_lookup(file, args->handle);
733 return -ENOENT;
736 args->flags = 0;
738 if (bo->flags & TEGRA_BO_BOTTOM_UP)
739 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
819 struct tegra_drm_file *fpriv = file->driver_priv;
821 mutex_lock(&fpriv->lock);
822 idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
824 mutex_unlock(&fpriv->lock);
826 idr_destroy(&fpriv->legacy_contexts);
827 mutex_destroy(&fpriv->lock);
834 struct drm_info_node *node = (struct drm_info_node *)s->private;
835 struct drm_device *drm = node->minor->dev;
838 mutex_lock(&drm->mode_config.fb_lock);
840 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
842 fb->base.id, fb->width, fb->height,
843 fb->format->depth,
844 fb->format->cpp[0] * 8,
848 mutex_unlock(&drm->mode_config.fb_lock);
855 struct drm_info_node *node = (struct drm_info_node *)s->private;
856 struct drm_device *drm = node->minor->dev;
857 struct tegra_drm *tegra = drm->dev_private;
860 if (tegra->domain) {
861 mutex_lock(&tegra->mm_lock);
862 drm_mm_print(&tegra->mm, &p);
863 mutex_unlock(&tegra->mm_lock);
878 minor->debugfs_root, minor);
917 client->shared_channel = host1x_channel_request(&client->base);
918 if (!client->shared_channel)
919 return -EBUSY;
921 mutex_lock(&tegra->clients_lock);
922 list_add_tail(&client->list, &tegra->clients);
923 client->drm = tegra;
924 mutex_unlock(&tegra->clients_lock);
932 mutex_lock(&tegra->clients_lock);
933 list_del_init(&client->list);
934 client->drm = NULL;
935 mutex_unlock(&tegra->clients_lock);
937 if (client->shared_channel)
938 host1x_channel_put(client->shared_channel);
945 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
946 struct drm_device *drm = dev_get_drvdata(client->host);
947 struct tegra_drm *tegra = drm->dev_private;
952 if (client->dev->archdata.mapping) {
954 to_dma_iommu_mapping(client->dev);
955 arm_iommu_detach_device(client->dev);
958 domain = iommu_get_domain_for_dev(client->dev);
965 * domain. This allows using the IOMMU-backed DMA API.
967 if (domain && domain->type != IOMMU_DOMAIN_IDENTITY &&
968 domain != tegra->domain)
971 if (tegra->domain) {
972 group = iommu_group_get(client->dev);
974 return -ENODEV;
976 if (domain != tegra->domain) {
977 err = iommu_attach_group(tegra->domain, group);
984 tegra->use_explicit_iommu = true;
987 client->group = group;
994 struct drm_device *drm = dev_get_drvdata(client->host);
995 struct tegra_drm *tegra = drm->dev_private;
998 if (client->group) {
1004 domain = iommu_get_domain_for_dev(client->dev);
1006 iommu_detach_group(tegra->domain, client->group);
1008 iommu_group_put(client->group);
1009 client->group = NULL;
1020 if (tegra->domain)
1021 size = iova_align(&tegra->carveout.domain, size);
1026 if (!tegra->domain) {
1028 * Many units only support 32-bit addresses, even on 64-bit
1029 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1031 * lower 32-bit range.
1038 return ERR_PTR(-ENOMEM);
1040 if (!tegra->domain) {
1049 alloc = alloc_iova(&tegra->carveout.domain,
1050 size >> tegra->carveout.shift,
1051 tegra->carveout.limit, true);
1053 err = -EBUSY;
1057 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1058 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1066 __free_iova(&tegra->carveout.domain, alloc);
1076 if (tegra->domain)
1077 size = iova_align(&tegra->carveout.domain, size);
1081 if (tegra->domain) {
1082 iommu_unmap(tegra->domain, dma, size);
1083 free_iova(&tegra->carveout.domain,
1084 iova_pfn(&tegra->carveout.domain, dma));
1092 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1101 * likely to be allocated beyond the 32-bit boundary if sufficient
1106 * 32-bit boundary.
1126 domain = iommu_get_domain_for_dev(dev->dev.parent);
1130 * 32-bit boundary, so the regular GATHER opcodes will always be
1142 struct device *dma_dev = dev->dev.parent;
1147 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1153 err = -ENOMEM;
1158 tegra->domain = iommu_paging_domain_alloc(dma_dev);
1159 if (IS_ERR(tegra->domain)) {
1160 err = PTR_ERR(tegra->domain);
1169 mutex_init(&tegra->clients_lock);
1170 INIT_LIST_HEAD(&tegra->clients);
1172 dev_set_drvdata(&dev->dev, drm);
1173 drm->dev_private = tegra;
1174 tegra->drm = drm;
1178 drm->mode_config.min_width = 0;
1179 drm->mode_config.min_height = 0;
1180 drm->mode_config.max_width = 0;
1181 drm->mode_config.max_height = 0;
1183 drm->mode_config.normalize_zpos = true;
1185 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1186 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1195 * Now that all display controller have been initialized, the maximum
1199 tegra->hmask = drm->mode_config.max_width - 1;
1200 tegra->vmask = drm->mode_config.max_height - 1;
1202 if (tegra->use_explicit_iommu) {
1204 u64 dma_mask = dma_get_mask(&dev->dev);
1208 start = tegra->domain->geometry.aperture_start & dma_mask;
1209 end = tegra->domain->geometry.aperture_end & dma_mask;
1212 gem_end = end - CARVEOUT_SZ;
1216 order = __ffs(tegra->domain->pgsize_bitmap);
1217 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1220 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1221 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1223 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1224 mutex_init(&tegra->mm_lock);
1227 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1228 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1230 } else if (tegra->domain) {
1231 iommu_domain_free(tegra->domain);
1232 tegra->domain = NULL;
1236 if (tegra->hub) {
1237 err = tegra_display_hub_prepare(tegra->hub);
1242 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1243 drm->max_vblank_count = 0xffffffff;
1245 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1247 goto hub;
1256 * Another case where this happens is on Tegra234 where the display
1260 if (drm->mode_config.num_crtc > 0) {
1263 goto hub;
1266 * Indicate to userspace that this doesn't expose any display
1269 drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1274 goto hub;
1280 hub:
1281 if (tegra->hub)
1282 tegra_display_hub_cleanup(tegra->hub);
1284 if (tegra->domain) {
1285 mutex_destroy(&tegra->mm_lock);
1286 drm_mm_takedown(&tegra->mm);
1287 put_iova_domain(&tegra->carveout.domain);
1296 if (tegra->domain)
1297 iommu_domain_free(tegra->domain);
1307 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1308 struct tegra_drm *tegra = drm->dev_private;
1317 if (tegra->hub)
1318 tegra_display_hub_cleanup(tegra->hub);
1322 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1324 if (tegra->domain) {
1325 mutex_destroy(&tegra->mm_lock);
1326 drm_mm_takedown(&tegra->mm);
1327 put_iova_domain(&tegra->carveout.domain);
1329 iommu_domain_free(tegra->domain);
1340 drm_atomic_helper_shutdown(dev_get_drvdata(&dev->dev));
1363 { .compatible = "nvidia,tegra20-dc", },
1364 { .compatible = "nvidia,tegra20-hdmi", },
1365 { .compatible = "nvidia,tegra20-gr2d", },
1366 { .compatible = "nvidia,tegra20-gr3d", },
1367 { .compatible = "nvidia,tegra30-dc", },
1368 { .compatible = "nvidia,tegra30-hdmi", },
1369 { .compatible = "nvidia,tegra30-gr2d", },
1370 { .compatible = "nvidia,tegra30-gr3d", },
1371 { .compatible = "nvidia,tegra114-dc", },
1372 { .compatible = "nvidia,tegra114-dsi", },
1373 { .compatible = "nvidia,tegra114-hdmi", },
1374 { .compatible = "nvidia,tegra114-gr2d", },
1375 { .compatible = "nvidia,tegra114-gr3d", },
1376 { .compatible = "nvidia,tegra124-dc", },
1377 { .compatible = "nvidia,tegra124-sor", },
1378 { .compatible = "nvidia,tegra124-hdmi", },
1379 { .compatible = "nvidia,tegra124-dsi", },
1380 { .compatible = "nvidia,tegra124-vic", },
1381 { .compatible = "nvidia,tegra132-dsi", },
1382 { .compatible = "nvidia,tegra210-dc", },
1383 { .compatible = "nvidia,tegra210-dsi", },
1384 { .compatible = "nvidia,tegra210-sor", },
1385 { .compatible = "nvidia,tegra210-sor1", },
1386 { .compatible = "nvidia,tegra210-vic", },
1387 { .compatible = "nvidia,tegra210-nvdec", },
1388 { .compatible = "nvidia,tegra186-display", },
1389 { .compatible = "nvidia,tegra186-dc", },
1390 { .compatible = "nvidia,tegra186-sor", },
1391 { .compatible = "nvidia,tegra186-sor1", },
1392 { .compatible = "nvidia,tegra186-vic", },
1393 { .compatible = "nvidia,tegra186-nvdec", },
1394 { .compatible = "nvidia,tegra194-display", },
1395 { .compatible = "nvidia,tegra194-dc", },
1396 { .compatible = "nvidia,tegra194-sor", },
1397 { .compatible = "nvidia,tegra194-vic", },
1398 { .compatible = "nvidia,tegra194-nvdec", },
1399 { .compatible = "nvidia,tegra234-vic", },
1400 { .compatible = "nvidia,tegra234-nvdec", },
1433 return -ENODEV;
1458 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");